an Intel company
2.5 Gbit/s
Retiming
Laser Driver
GD16578
Preliminary
General Description
The GD16578 is a high performance low
power 2.5 Gbit/s Laser Driver with
optional on chip retiming of data.
The GD16578 is designed to meet and
exceed ITU-T STM-16 or SONET OC-48
fiberoptic communication systems re-
quirements.
The GD16578 is designed to sink a
Modulation Current into the IOUT pin and
a Pre-Bias Current into the IPRE pin. The
Modulation Current is adjustable up to
200 mA by means of the pin VMOD. The
Pre-Bias Current may be adjusted up to
60 mA by means of the VPRE pin.
Retiming of the data signal connected to
the pins DIN, DINQ is made by means of
a DFF clocked by an external clock sig-
nal at the data rate fed to the pins CKIN
and CKINQ.
A Mark-Space monitor is available on the
pins MARKP and MARKN. Together with
the symmetry adjustment pin (SYM) this
may be used to control the mark space
ratio of the output signal.
The GD16578 can operate on a single
+5 V supply or a single -5.2 V supply.
The circuit is available in a thermally
enhanced 32-pin TQFP plastic package.
Features
l
Complies with ITU-T STM-16 and
SONET OC-48 standards.
Intended for driving a 25
W
load, e.g.
a laser diode or Mach Zender modu-
lator with 25
W
input impedance.
Clocked or non-clocked operation.
Large modulation current adjustment
range from 70 mA to 200 mA.
Output voltage over / under shoot
less than
±5
% respectively
±10
%.
Rise / fall times less than 100 ps.
Laser diode pre-bias adjustable up to
60 mA.
Mark-Space monitor.
Symmetry adjustment
Internal 50
W
termination of data and
clock inputs.
Power dissipation: 1 W (typ.).
(excluding Modulation Current and
Pre-bias Current).
32 pin thermally enhanced TQFP
plastic package.
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VMOD
VPRE
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Modulation
Current
Control
CKSEL
SPOL
DIN
DINQ
50
50
Pre-Bias
Current
Control
IPRE
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VDD
VDDR
IOUT
Output
Driver
IOUTN
VEE
VEEB
VEEP
VEER
MARKP
Input
Buffer
Mark/Space
Monitor
MARKN
SYM
MUX
D
Q
Input
Buffer
Applications
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DINT
CKIN
CKINQ
50
50
Tele Communication:
– SDH STM-16
– SONET OC-48
Data Communication.
Electro Absorption laser driver.
Direct Modulation laser driver.
Mach Zender modulator driver.
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CKINT
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Data Sheet Rev.: 10
Functional Details
GD16578 is a 2.5 Gbit/s laser driver with
an optional retiming of the data signal. It
is capable of driving high power laser di-
odes, typically having input impedance of
25
W,
at a maximum modulation current
of 200 mA and a maximum pre-bias cur-
rent of 60 mA.
Data (DIN, DINQ) is input to GD16578
and retimed within a DFF clocked by an
external clock (CKIN, CKINQ). Optionally
the retiming may be bypassed controlled
by a select pin (CKSEL).
Both the differential data (DIN, DINQ)
and clock inputs (CKIN, CKINQ) are in-
ternally terminated to 50
W.
Termination
is made with a 50
W
resistor from the two
differential inputs to a common pin called
DINT and CKINT respectively. Each of
these termination pins is DC biased inter-
nally via 750
W
to -1.3 V, hence there is
no need for external bias network. The
input sensitivity when driven with a single
ended signal is better than 150 mV on
both clock and data inputs.
The GD16578 can be used e.g. to boost
the output from the GD16553 MUX. This
differential output can be DC coupled to
the GD16578 input. A signal of 200 mV
PP
at a common mode level of -100 mV has
been observed to provide good perfor-
mance.
The output pin (IOUT) is an open collec-
tor output designed for driving external
loads with 25
W
characteristic imped-
ance. Because of the nature of an open
collector the output therefore may be re-
garded as a current switch, with infinite
output impedance. The characteristic im-
pedance through the package is approxi-
mately 25
W.
Optimum performance of
GD16578 therefore is achieved if the out-
put is terminated into a 25
W
impedance.
The output modulation current is con-
trolled by the pin VMOD and can be con-
trolled in the range from 0 mA to 200 mA,
however the specifications is only valid in
the range from 70 mA to 200 mA. The
output voltage swing across the external
load may be varied accordingly. The
modulation current control on pin VMOD
is implemented as a current mirror and
therefore sinks a current proportional to
the modulation current. The current sink
into the VMOD pin is approximately
1/210 of the modulation current.
VMOD
2kW
2V
VEE
Figure 2.
Equivalent schematic of the
VMOD input
When DC coupled the output swing will
be limited by the specification for the
minimum voltage of
V
DD
-3 V on the
IOUT and IOUTN pins. Since 120 mA
into 25
W
gives 3 V swing it will not be
possible to terminate the output with a
25
W
load to
V
DD
.
If more than 120 mA modulation current
is required, either the load (i.e. the laser)
must be supplied from a positive supply
voltage, or AC coupling with a bias tee
must be used (see
Figure 3).
Control Voltage from
Modulation Current
Control System
Control Voltage from
Pre-Bias Current
Control System
VMOD / 20
VPRE / 16
Laser Diode Equivalent
25
W
Input Impedance
Modulation
Current
Control
CKSEL / 1
SPOL / 9
50
50
Pre-Bias
Current
Control
IPRE / 19
VTT
L
C
25
25
Differential or
Single-ended
Data Signal
DIN / 27
MUX
DINQ / 26
50
50
750
D
100n
50
50
DINT / 28
Input
Buffer
-1.3V
Q
IOUT / 13, 14
Output
Driver
IOUTN / 11, 12
C
25
L
VDD
Differential or
Single-ended
Clock Signal
CKIN / 31
CKINQ / 32
50
50
750
VTT
MARKP / 7
Input
Buffer
-1.3V
100n
Mark/Space
MARKN / 6
Monitor
VEEP / 18
-
+
Ref.
100n
CKINT / 30
Negative
Supply
Figure 1.
Application Diagram
Data Sheet Rev.: 10
GD16578
Page 2 of 10
VTT
L1
220uH
L3
220uH
VTT
L2
10uH
L4
10uH
100nF
100nF
25W
VDD
To
Ext.
Load
IOUT
IOUTN
An important parameter for laser drivers
is voltage overshoot on the output pin
(IOUT), because it determines the extinc-
tion ratio. GD16578 has been designed
with special emphasis on achieving a
very small voltage overshoot. For
GD16578 the voltage overshoot is less
than 5 % across the full modulation cur-
rent range, when driving a 25
W
load.
Similarly the voltage undershoot is less
than 10 %.
A mark-space monitor is provided
through the pins MARKP and MARKN.
These may be connected as shown in
the application diagram below, with a ca-
pacitor across the two outputs and a
comparator (or Op-amp) to determine the
mark density. Symmetry input (SYM) is
available which may be used to control
the mark-space ratio.
Figure 3.
AC Coupled Output
For high modulation currents it may be
necessary to use a positive supply for the
bias tee, depending on the resistance in
the bias coils. Measurements with the
set-up in
Figure 3
with bias coils with 7
W
resistance show that a positive supply is
required for modulation current above
approximately 150 mA, and a voltage
V
TT
= +1,0 V is sufficient to give 200 mA
with
V
EE
= –5.2 V supply. Less negative
V
EE
voltage must be compensated by
correspondingly higher
V
TT
supply.
In the configuration shown in
Figure 3
two coils in series are used for each
branch of the output for effective blocking
of high and low frequencies. Low fre-
quency ciols generally have high para-
sitic parallel capacitance.
Figure 4.
Output waveform at 200 mA,
-4.7 V supply, AC coupled
load.
The pre-bias current is controlled by the
pin VPRE and can be controlled from
0 mA to 60 mA. The pre-bias current
control on pin VPRE is implemented as a
current mirror and therefore sinks a cur-
rent proportional to the pre-bias current.
The current sink into the VPRE pin is
approximately 3/500 of the pre-bias
current.
Data Sheet Rev.: 10
GD16578
Page 3 of 10
Pin List
Mnemonic:
DIN
DINQ
DINT
CKIN
CKINQ
CKINT
IOUT
IOUTN
IPRE
VMOD
Pin No.:
27
26
28
31
32
30
13, 14
11, 12
19
20
Pin Type:
AC IN
ANL IN
AC IN
ANL IN
OPEN
COLLECTOR
OPEN
COLLECTOR
ANL IN
Description:
Data inputs. Internally terminated in 50
W
to DINT.
Termination voltage for DIN and DINQ.
Internally biased to -1.3 V with 750
W.
Clock inputs. Internally terminated in 50
W
to CKINT. Data is sam-
pled on the positive going edge of the clock (CKIN).
Termination voltage for CKIN and CKINQ.
Internally biased to -1.3 V with 750
W.
Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modula-
tion current, which is controlled by the pin VMOD. The polarity of
the output depends on the settings of SPOL, see below.
Pre-bias current output. IPRE sinks a current, which is controlled
by the pin VPRE.
Modulation current control input. The control system is made as a
current mirror. VMOD sinks a current proportional to the modula-
tion current. This current is approximately 1/210 times “The modu-
lation current”.
Pre-bias current control input. The control system is made as a
current mirror. VPRE sinks a current proportional to the pre-bias
current. This current is approximately 3/500 times “The pre-bias
current”.
When CKSEL is low data is retimed. Otherwise data is bypassed
the retiming. May be connected to rails.
Data polarity select pin. When SPOL is high, a high level on DIN
will cause the IOUT output to sink current, i.e. causing the voltage
on IOUT to be low. SPOL is internally pulled to VDD with a 5 k re-
sistor. May be connected to rails.
SYM controls the mark-space ratio of the output. Decreasing the
voltage of the SYM pin decreases the pulse width of a current
high into the IOUT pin. When SYM is left open the output cross-
over will be 50%.
Mark-space monitor outputs. High impedance CML outputs. The
output voltage of the MARKP pin is the same polarity as the volt-
age on the IOUT pin.
Ground pins for laser driver part.
Ground pin for retiming part.
Negative supply pins for laser driver part. Package back is VEE.
Negative supply pin for pre-bias circuitry.
Negative supply pin for output driver.
Negative supply pin for retiming part.
Not Connected.
Connected to VEE.
VPRE
16
ANL IN
CKSEL
SPOL
1
9
ECL IN
ECL IN
SYM
24
ANL IN
MARKP
MARKN
VDD
VDDR
VEE
VEEB
VEEP
VEER
NC
Heat sink
7
6
2, 3, 4, 10, 15
29
5, 8, 23
17
18
25
21, 22
Package back
ANL OUT
PWR
PWR
PWR
PWR
PWR
PWR
Data Sheet Rev.: 10
GD16578
Page 4 of 10
Package Pinout
CKINQ
32
CKINT
30
VDDR
VEER
DINQ
CKIN
31
DINT
28
DIN
27
25
26
29
CKSEL
VDD
VDD
VDD
VEE
MARKN
MARKP
VEE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SYM
VEE
NC
NC
VMOD
IPRE
VEEP
VEEB
16
15
14
13
12
10
11
9
VPRE
VDD
IOUT
IOUT
IOUTN
IOUTN
VDD
SPOL
Figure 5.
Package 32 TQFP, Top View
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in table are referred to VDD.
All currents in table are defined positive out of the pin.
Symbol:
V
EE
V
O
V
O
IOUT/N
V
I
I
I
AC IN
I
I
VMOD
I
I
VPRE
T
O
T
S
Note 1:
Characteristic:
Power Supply
Applied Voltage (All Outputs)
Applied Voltage IOUT and IOUTN
Applied Voltage (All Inputs)
Input Current (AC IN)
Input Current (VMOD)
Input Current (VPRE)
Operating Temperature
Storage Temperature
Voltage and/or current should be externally limited to specified range.
GD16578
Page 5 of 10
Note 1
Case
Conditions:
MIN.:
-6
V
EE
-0.5
V
EE
-0.5
V
EE
-0.5
-1
-2
-1
-40
-65
TYP.:
MAX.:
0
0.5
3
0.5
1
0.1
1
+110
+125
UNIT:
V
V
V
V
mA
mA
mA
°C
°C
Data Sheet Rev.: 10
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