ZL30415
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
•
•
•
Meets jitter requirements of Telcordia GR-253-
CORE for OC-12, OC-3, and OC-1 rates
Meets jitter requirements of ITU-T G.813 for STM-
4, and STM-1 rates
Provides one differential LVPECL output clock
selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, or 622.08 MHz
Provides a single-ended CMOS output clock at
19.44 MHz
Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL, or
CML reference at 19.44 MHz or 77.76 MHz
Provides a LOCK indication
3.3 V supply
Ordering Information
ZL30415GGC
ZL30415GGC2
64 Ball CABGA
64 Ball CABGA*
June 2005
*Pb-free Tin/Silver/Copper
-40°C to +85°C
•
•
Description
The ZL30415 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30415 generates low
jitter output clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates
and ITU-T G.813 STM-4 and STM-1 rates.
The ZL30415 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL, or CML
reference at 19.44 MHz or 77.76 MHz and generates a
differential LVPECL output clock selectable to
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or
622.08 MHz, and a single-ended CMOS clock at
19.44 MHz. The ZL30415 provides a lock indication.
•
•
Applications
•
SONET/SDH line cards
REF_SEL
LPF
FS3
FS2 FS1
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
C19i
Reference
Selection
MUX
Frequency
& Phase
Detector
Loop
Filter
VCO
REFinP/N
19.44 MHz and 77.76 MHz
State
Machine
Reference
and
Bias Circuit
Frequency
Dividers
and
Clock
Drivers
OC-CLKoP/N
C19o
C19i or C77i
CML, LVDS,
LVPECL input
REF_FREQ
LOCK
BIAS
VCC
GND
VDD
C19oEN
03
Figure 1 - Functional Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30415
Data Sheet
1
1
2
3
4
5
6
7
8
A
NC
NC
NC OC-CLKoP OC-CLKoN GND
NC
NC
B
NC
NC
VCC1
GND
NC
GND
GND
VCC
C
GND
VCC2
GND
GND
GND
NC
VDD
GND
D
BIAS
LPF
NC
GND
VCC
VCC
GND
GND
E
LOCK
NC
NC
FS2
VCC
VDD
NC
REFinN
F
NC
NC REF_FREQ C19oEN
C19i
C19o
GND
REFinP
G
GND
VDD
REF_SEL
FS3
GND
GND
VDD
VDD
H
NC
NC
NC
VDD
FS1
VDD
GND
GND
1
- A1 corner is identified by metallized markings.
8 mm x 8 mm
Ball Pitch 0.8 mm
Figure 2 - BGA 64 Ball Package (Top View)
1.0
Ball Description
Ball Description Table
Ball #
A1, A2
A3
A4
A5
Name
NC
OC-CLKoP
OC-CLKoN
Description
No internal bonding Connection.
Leave unconnected.
SONET/SDH Clock (LVPECL Output).
These outputs provide a selectable
differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1
inputs.
Ground.
0 volt
No internal bonding Connection.
Leave unconnected.
Positive Analog Power Supply.
+3.3 V +/-10%
Ground.
0 volt
No internal bonding Connection.
Leave unconnected.
A6
A7, A8
B1, B2
B3
B4
B5
GND
NC
VCC1
GND
NC
2
Zarlink Semiconductor Inc.
ZL30415
Ball Description Table (continued)
Ball #
B6, B7
B8
C1
C2
C3, C4
C5
C6
C7
C8
D1
D2
D3
D4
D5, D6
D7, D8
E1
E2, E3
E4
G4
H5
E5
E6
E7
E8
F8
Name
GND
VCC
GND
VCC2
GND
NC
VDD
GND
BIAS
LPF
NC
GND
VCC
GND
LOCK
NC
FS2
FS3
FS1
VCC
VDD
NC
REFinN
REFinP
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%
Ground.
0 volt
No internal bonding Connection.
Leave unconnected.
Positive Digital Power Supply.
+3.3 V ±10%
Ground.
0 volt
Bias Circuit.
Description
Data Sheet
External Low-Pass Filter
(Analog). Connect external RC network for the low-
pass filter.
No internal bonding Connection.
Leave unconnected.
Ground.
0 volt
Positive Analog Power Supply.
+3.3 V ±10%
Ground.
0 volt
Lock Indicator (CMOS Output).
This output goes high when the PLL is
frequency locked to the selected input reference.
No internal bonding Connection.
Leave unconnected.
Frequency Select 3-1 (CMOS Input).
These inputs select the clock frequency
on the OC-CLKo output. The possible output frequencies are:
19.44 MHz (000), 38.88 MHz (001), 77.76 MHz (010), 155.52 MHz (011),
622.08 (100)
Positive Analog Power Supply.
+3.3 V ±10%
Positive Digital Power Supply.
+3.3 V ±10%
No internal bonding Connection.
Leave unconnected.
Differential Reference Clock Input (CML/LVDS/LVPECL Compatible Input).
These inputs accept a differential clock at 77.76 MHz or 19.44 MHz as the
reference for synchronization. These inputs do not have on-chip AC coupling
capacitors.
No internal bonding Connection.
Leave unconnected.
Reference Frequency (CMOS Input).
This input selects the rate of the
differential input clock (REFinP/N) to be either 77.76 MHz or 19.44 MHz.
C19o Output Enable (CMOS Input).
If tied high this control input enables the
C19o output clock. Pulling this pin low forces the output driver into a high
impedance state.
F1, F2
F3
F4
NC
REF_FREQ
C19oEN
3
Zarlink Semiconductor Inc.
ZL30415
Ball Description Table (continued)
Ball #
F5
F6
F7, G1
G2
G3
Name
C19i
C19o
GND
VDD
REF_SEL
Description
Data Sheet
C19 Reference Input (CMOS Input).
This is a single-ended input reference
source used for synchronization. This input accepts 19.44 MHz.
Clock 19.44 MHz (CMOS Output).
This output provides a single-ended CMOS
clock at 19.44 MHz.
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
Reference Select (CMOS Input).
If tied low then the C19i single-ended
reference is used as the input reference source. If tied high then the REFinP/N
differential pair is used as the input reference source.
See E4 ball description.
Ground.
0 volt
Positive Digital Power Supply.
+3.3 V ±10%
No internal bonding Connection.
Leave unconnected.
Positive Digital Power Supply.
+3.3 V ±10%
See E4 ball description.
Positive Digital Power Supply.
+3.3 V ±10%
Ground.
0 volt.
G4
G5, G6
G7, G8
H1, H2
H3
H4
H5
H6
H7, H8
FS3
GND
VDD
NC
VDD
FS1
VDD
GND
2.0
Functional Description
The ZL30415 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30415 is shown in
Figure 1 and a brief description is presented in the following sections.
2.1
Reference Selection Multiplexer
The ZL30415 accepts two types of input reference clocks:
-
-
differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels
single-ended: operating at 19.44 MHz, compatible with CMOS switching levels.
The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential
reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the
differential input clock to be either 19.44 MHz, or 77.76 MHz. See Table 1 for details.
REF_SEL
0
1
1
REF_FREQ
x
0
1
Selected Input Reference
C19i
REFin
REFin
Reference Frequency
19.44 MHz (CMOS)
77.76 MHz (Differential)
19.44 MHz (Differential)
Table 1 - Input Reference Selection
4
Zarlink Semiconductor Inc.
ZL30415
2.2
Frequency/Phase Detector
Data Sheet
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit.
2.3
Lock Indicator
The ZL30415 has a built-in LOCK detector that measures frequency difference between input reference clock C19i
and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency
then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm.
2.4
Loop Filter
The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase
error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements.
The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF
ball and ground as shown in Figure 3.
ZL30415
Frequency
and Phase
Detector
LPF
Loop
Filter
R
F
C
F
R
F
=8.2 kΩ, C
F
=470 nF
VCO
Figure 3 - Loop Filter Elements
2.5
VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
5
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