ZL20250
2.5G Multimode Transceiver
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
Quad Band GSM (800/900/1800/1900 MHz)
Compatible
Dual Band IS136 (800/1900 MHz) Compatible
GPRS Class 12 and EDGE Capable
Fully Integrated Dual Band Transceiver
Receive - IF to Baseband I and Q
Transmit - Baseband I / Q to RF
Integrated Filters
FM Demodulator
RF and IF Synthesizers
Fully Programmable via serial bus
3 Volt operation
Small scale package
Ordering Information
ZL20250/LCE (Tubes) 56 pin QFN
ZL20250/LCF (Tape and Reel) 56 pin QFN
-40°C to +85°C
September 2003
Description
The ZL20250 is a fully integrated transceiver for
multimode IS136/GSM/GPRS/EDGE handsets. The
dual IF inputs to the receive path are amplified and
down-converted to baseband I and Q signals. Gain
control and baseband filtering are provided. A FM
demodulator is also provided where AMPS
compatibility is required.
The transmit path consists of a quadrature modulator,
gain control at IF and up-conversion to RF. Dual band
RF outputs are provided.
ZL20250 also includes a fractional N RF synthesizer
and two IF synthesizers to provide all local oscillator
signals required.
Flexible programming is provided via a 3 wire serial
bus. Additional control pins allow accurate timing
control when switching between modes.
Applications
•
•
•
•
•
•
GAIT IS136/GSM/EDGE Mobile Telephones
Dual Band (850/PCS1900) TDMA/AMPS Mobile
Telephones
Cellular 850MHz TDMA/AMPS Mobile
Telephones
PCS1900 TDMA Mobile Telephones
2.5G World Phones - Quad Band
(850/900/1800/1900)
Cellular Telematic Systems
GSM/EDGE
Rx I
90°
Rx Q
IS136
FM
Demod
Rx VHF
PLL
Serial
Interface
Control
FM
RSSI
LOCK DET
UHF LO O/P
UHF VCO
UHF
PLL
Tx VHF
PLL
900 MHz Tx
IQ
Mod
1900 MHz Tx
Tx I
Tx Q
Tx IF Filter
(Opt)
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZL20250
Pin Description Table
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pin Name
SDAT
SCLK
SLATCH
TCXO
VCC UHF PLL
UHF CP
900 LO OUT
1900 LO OUT
RESETB
ENABLE1
900 LO IN
VCC UHF LO
1900 LO IN
VCC TX RF
TX 900
TX DEG900
TX DEG1900
TX 1900
ENABLE2
TX GAIN
TX FILT IN+
TX FILT IN-
VCC TX
TX FILT OUT+
TX FILT OUT-
TX Q+
TX Q-
TX VCO+
TX VCO-
VCC TX PLL
TX I+
TX I-
TX RXB
TX CP
LOCK DET
ISET
VCC VHF CP
Power
Power
Input
Input
Input
Output
Output
Transmit / Receive control
Transmit VHF PLL charge pump output
PLL Lock Detect Output
Power to Transmit VHF PLL
I transmit signal from baseband
Output
Input
Input
Input
Input
Power
Output
Output
Input
Input
Transmit Oscillator tank circuit
Q transmit signal from baseband
Power to transmit stages
Output to transmit IF filter (optional)
Type
Input
Input
Input
Input
Power
Output
Output
Output
Input
Input
Input
Power
Input
Power
Output
Serial Interface - Data
Serial interface - Clock
Serial Interface - Latch
Reference input from TCXO
Power
UHF PLL Charge Pump Output
Power to LO output stages
900 MHz buffered LO output to external receiver mixer
1900 MHz buffered LO output to external receiver mixer
Reset (Active low)
Mode Control
900 MHz LO input
Power to UHF LO input stage
1900 MHz LO input
Power to transmit RF output stages
900 MHz transmit output
Degeneration for 900 MHz output
Degeneration for 1900 MHz output
1900 MHz transmit output
Mode Control
Transmit gain control
Input from transmit IF filter (optional)
Description
Data Sheet
VCC UHF LO OUT Power
Connect 50 kohm resistor to ground to set internal reference current
Power to VHF charge pump outputs
3
Zarlink Semiconductor Inc.
ZL20250
Table of Contents
Data Sheet
1.0 General Description ......................................................................................................................................... 8
1.1 Receive Path ............................................................................................................................................... 9
1.1.1 IS136.................................................................................................................................................. 9
1.1.2 AMPS FM......................................................................................................................................... 11
1.1.3 GSM ................................................................................................................................................. 14
1.2 Transmit..................................................................................................................................................... 16
1.3 UHF LO and Frequency Doubler............................................................................................................... 19
1.4 UHF Frequency Synthesizer ..................................................................................................................... 19
1.5 VHF Frequency Synthesizer...................................................................................................................... 22
1.6 Internal Clock Generation.......................................................................................................................... 23
1.7 VHF VCO................................................................................................................................................... 23
1.8 Power Supply Connections ....................................................................................................................... 24
2.0 Programming and Control ............................................................................................................................ 25
2.1 Power Control Registers - Address 0 to 3 ................................................................................................. 25
2.1.1 Power Control Modes - TDMA (GSM and IS136) ............................................................................ 27
2.1.2 Power Control Modes - AMPS ......................................................................................................... 28
2.2 Operating Register Address 4 ................................................................................................................... 29
2.3 Synthesizer Register - Address 5 .............................................................................................................. 33
2.3.1 UHF PLL and LO.............................................................................................................................. 33
2.3.2 UHF PLL Charge Pump Current ...................................................................................................... 34
2.3.3 Receive LO Set Up .......................................................................................................................... 34
2.3.4 Transmit LO Set Up ......................................................................................................................... 35
2.4 Control Register - Address 6 ..................................................................................................................... 35
2.4.1 IS136 Baseband Gain ...................................................................................................................... 35
2.4.2 TCXO Reference Selection............................................................................................................. 36
2.4.3 Discriminator Output Filtering........................................................................................................... 36
2.4.4 Transmit baseband Gain.................................................................................................................. 37
2.4.5 Mode Control.................................................................................................................................... 37
2.5 GSM/EDGE Baseband Control Register - Address 7................................................................................ 37
2.5.1 Q Channel Gain Adjust .................................................................................................................... 38
2.5.2 Baseband Offset Correction............................................................................................................. 38
2.6 Test Mode Register - Address 8................................................................................................................ 38
2.7 UHF PLL Divider Programming Register - Address 9 ............................................................................... 39
2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10 ................................ 39
2.9 Receive VHF PLL Divider Programming Register - Address 11 ............................................................... 39
2.10 Receive VHF PLL Reference Divider Programming Register - Address 12............................................ 40
2.11 Transmit VHF PLL Divider Programming Register - Address 13 ............................................................ 40
2.12 Transmit VHF PLL Reference Divider Programming Register Address 14 ............................................. 40
2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15 .............................. 40
2.13.1 Fractional N Compensation............................................................................................................ 41
2.13.2 PLL Lock detect counters............................................................................................................... 41
3.0 Absolute Maximum Ratings .......................................................................................................................... 41
4.0 Operating Conditions .................................................................................................................................... 41
5.0 Electrical Characteristics .............................................................................................................................. 43
6.0 Typical Performance Curves ........................................................................................................................ 51
6.1 Receive...................................................................................................................................................... 51
6.2 Transmit..................................................................................................................................................... 52
5
Zarlink Semiconductor Inc.
京公网安备 11010802033920号
EEWORLD
