ZL30110LDG1 datasheet, PDF - EEWORLD Datasheet

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ZL30110LDG1: DescriptionTelecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32; CategoryWireless rf/communication Telecom circuit; File Size215KB，22 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/; Environmental Compliance

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ZL30110LDG1 Overview

Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32

ZL30110LDG1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Zarlink Semiconductor (Microsemi)
package instruction	HVQCCN, LCC32,.2SQ,20
Reach Compliance Code	unknown
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Number of functions	1
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	0.9 mm
Maximum slew rate	0.115 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	5 mm

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ZL30110

Telecom Rate Conversion DPLL

Data Sheet

Features

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

16.384 MHz

Provides a range of output clocks:

•

65.536 MHz TDM clock locked to the input

reference

General purpose 25 MHz fan-out to 6 outputs

locked to the external crystal or oscillator

General purpose 125 MHz and 66 MHz or

100 MHz locked to the external crystal or

oscillator

Ordering Information

ZL30110LDE

ZL30110LDG1

ZL30110LDF1

32 Pin QFN

32 Pin QFN*

Tubes, Bake & Dry Pack

Trays, Bake & Dry Pack

Tape & Reel

May 2009

*Pb Free Matte Tin

-40°C to +85°C

Applications

•

Clock rate conversion PLL for Telecommunication

Equipment

Small/Medium Enterprise Router / Gateway

Broadband access (xPON/xDSL) CPE gateway

•

Provides DPLL lock and reference fail indication

Automatic free run mode on reference fail

DPLL bandwidth of 922 Hz for all rates of input

reference and 58 Hz for an 8 kHz input reference

Less than 5 psec

rms

on 25 MHz outputs, and less

than 0.6 ns

intrinsic jitter on the all other outputs

Minimal input to output and output to output skew

25 MHz external master clock source: clock

oscillator or crystal

Simple hardware control interface

Description

The ZL30110 clock rate conversion digital phase-

locked loop (DPLL) provides accurate and reliable

frequency conversion.

The ZL30110 generates a range of clocks that are

either locked to the input reference or locked to the

external crystal or oscillator.

In the locked mode, the reference input is continuously

monitored for a failure condition. In the event of a

failure, the DPLL continues to provide a stable free

running clock ensuring system reliability.

REF_FAIL

LOCK

REF

Reference

Monitor

State Machine

DPLL

Frequency

Synthesizer

C65o

RST

Select MUX

OUT_SEL

OSCi

OSCo

Master

Clock

APLL

C100/66o

C125o

6 X C25o

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL30110

Table of Contents

Data Sheet

1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5 APLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.0 DPLL Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.0 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Zarlink Semiconductor Inc.

ZL30110LDG1 Related Products

	ZL30110LDG1	ZL30110LDF1
Description	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32	Telecom Circuit, 1-Func, 5 X 5 MM, LEAD FREE, MO-220, QFN-32
Is it Rohs certified?	conform to	conform to
Maker	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	HVQCCN, LCC32,.2SQ,20	HVQCCN, LCC32,.2SQ,20
Reach Compliance Code	unknown	unknown
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e3
length	5 mm	5 mm
Number of functions	1	1
Number of terminals	32	32
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20	LCC32,.2SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
power supply	1.8,3.3 V	1.8,3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	0.9 mm	0.9 mm
Maximum slew rate	0.115 mA	0.115 mA
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	MATTE TIN
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	5 mm	5 mm

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