ZL50402
Managed 2FE + 1GE Layer-2
Ethernet Switch
Data Sheet
Zarlink Features
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Integrated Single-Chip 10/100/1000 Mbps
Ethernet Switch
• Two 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
Embedded 2.0 Mbits (256 KBytes) internal
memory for control databases and frame data
buffer
• Supports jumbo frames up to 4 KBytes
CPU access supports the following interface
options:
• 8/16-bit ISA interface
• Serial interface with MII port; recommended
for light management
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I
2
C EEPROM
interface
Ethernet IEEE 802.3x flow control for full duplex
ports, back pressure flow control for half duplex
ports
8/16-bit
or
Serial
August 2006
Ordering Information
ZL50402GDG
ZL50402GDG2
208-Ball LBGA
208-Ball LBGA**
**Pb Free Tin/Silver/Copper
-40°C to +85°C
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Built-in reset logic triggered by system
malfunction
Built-In Self Test for internal SRAM
IEEE-1149.1 (JTAG) test port
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L2 Switching
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L2 switching
• MAC address self learning, up to 4 K MAC
addresses
• MAC address table supports unicast and
multicast MAC address and IP multicast
address learning
Supports IP Multicast with IGMP snooping, up to
4 K IP Multicast groups
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C
P
U
ZL50402
MII
GM II / M II
2-Port 10/100M + 1G
Ethernet Switch
EEPROM
I
2
C
10/100/
1000
PHY
RM II / M II / GPSI
Dual
10/100
PHY
Figure 1 - System Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50402
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Supports the following spanning standards
• IEEE 802.1D spanning tree
• IEEE 802.1w rapid spanning tree
Supports Ethernet multicasting and broadcasting and flooding control
Data Sheet
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VLAN Support Features
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Supports the following VLAN standards
• port-based VLAN
• IEEE 802.1Q tag-based VLAN, up to 4 K VLANs
Supports both shared VLAN learning (SVL) and independent VLAN learning (IVL) of MAC addresses
Limited support for VLAN stacking (“Q-in-Q”)
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Classification and Security
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Search engine classification
• Classifies packets based on single field
- Source and destination L4 logical ports, or
- TOS/DS, or
- VLAN (IEEE 802.1p), or
- Physical port
• Assigns a transmission priority and drop precedence
Packet filtering and security
• Static address filtering for source and/or destination MAC addresses
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning (each port may independently use this mode)
• IEEE 802.1x access control
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of port VLAN ID
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Traffic Management
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Two (2) transmission classes for FE ports and four (4) transmission classes for uplink port
Scheduling using weighted fair queuing (WFQ) or strict priority (SP) discipline
At egress, per-queue weighted random early discard (WRED) with 2 drop precedence levels
• Configurable WRED thresholds
For FE ports, supports ingress and egress rate control
• Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement)
• Granularity of rate regulation to 16 Kbps
• Ingress rate regulated using WRED, with 2 drop precedence levels, or flow control
Output traffic regulation per class available on uplink port
Fully supports Differentiated Services' Expedited and Assured Forwarding (EF and AF) per-hop behaviours
Intelligent buffer management
• Achieves high buffer utilization while ensuring fairness among traffic classes and ports
• Buffer reservations per class and per source port
Supports concentration mode
Traffic Mirroring
• Physical port based (RMII enabled ports only)
• Source or destination MAC address based
• MAC address pair based
Supports module hot swap on all ports
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Zarlink Semiconductor Inc.
ZL50402
Network Management Support
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Built-in RMON MIB counters
Data Sheet
Description
The ZL50402 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 2 ports at 10/100 Mbps, 1 uplink port at 10/100/1000 Mbps, and a CPU interface for managed, lightly
managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and up to 4 K
tagged-based Virtual LANs (VLANs).
With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50402 provides
powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission
priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission
priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or
the UDP/TCP logical port fields in IP packets. The ZL50402 recognizes a total of 16 UDP/TCP logical ports, 8
hard-wired and 8 programmable (including one programmable range).
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50402 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network
management solution.
The ZL50402 is fabricated using 0.18 micron technology. The ZL50402 is packaged in a 208-pin Ball Grid Array
package.
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Zarlink Semiconductor Inc.
ZL50402
Changes Summary
July 2003
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Initial Release
Data Sheet
November 2003
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Clarified IP Multicast support is up to 4K groups, as it wasn’t mentioned in the data sheets
Updated Ball Signal Description Table (1.3, “Ball Signal Descriptions“ on page 14):
• clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs
OR
outputs
• clarified that M9_MTXCLK is an input only
Updated 1.4, “Signal Mapping and Internal pull-up/Down Configuration“ on page 20 to indicate operation of
the internal pull-up/down resistors in different modes
Clarified 9.1.3, “GMAC Reference Clock (GREF_CLK) Speed Requirement“ on page 52 on usage of
GREF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
I
2
C address mapping was corrected for QOSCn registers
Added Maximum Junction Temperature to 12.1, “Absolute Maximum Ratings“ on page 122
Updated I/O voltage levels to use TTL spec values rather than % of Vcc (12.2, “DC Electrical
Characteristics“ on page 122)
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February 2004
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Added the following to the Feature List:
• 4 K jumbo frames
• IEEE 802.3ad support
• Reverse MII/GPSI
Added section on PHY addresses (2.2.4, “PHY Addresses“ on page 28)
• Clarified that they are hard-coded
Fixed error in DS on sending Ethernet Frames via 8/16-bit or serial interface.
• The Status Bytes is sent before the frame, for both Tx and Rx
Added more cross-references to available AppNotes
Added section on Stacked VLAN (Q-in-Q) (5.9.3, “VLAN Stacking (Q-in-Q)“ on page 43) and IP Multicast
Switching (5.10, “IP Multicast Switching“ on page 44) since they weren’t really discussed in the DS
Added more clock descriptions to 9.0, “Clocks“ on page 52
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
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August 2004
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Added section Changes Summary to document
Added section on SCL clock generation (9.2.2, “SCL“ on page 52)
Interrupt Register was incorrectly identified as read only, should be read/write
• Clarified that only bit [7] is not self-clearing
Updated CPU timing diagrams to clarify timing (12.4, “AC Characteristics and Timing“ on page 124)
November 2004
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Added section 1.6, “Default Switch Configuration and Initialization Sequence“ on page 24
Updated CPU timing diagrams to clarify P_A timing (12.4, “AC Characteristics and Timing“ on page 124)
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Zarlink Semiconductor Inc.
ZL50402
January 2005
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Data Sheet
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Updated GMII timing (12.4.11, “Gigabit Media Independent Interface (GMII)“ on page 134)
• reduce min. hold time from 1ns to 0.5ns
• reduced max. output delay by 1ns
Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
June 2005
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Added 2FE+1GE variant
Corrected ordering code to ZL50402GD”G”
Clarified that port mirroring is only available if the source & destination ports are in RMII mode
Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F
Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap
TSTOUT[0]
Added power sequencing recommendation (1.7, “Power Sequencing“ on page 26)
Added Reverse MII/GPSI timing characteristics (12.4.10, “Reverse General Purpose Serial Interface
(RvGPSI)“ on page 133 and 12.4.12, “MII Management Data Interface (MDIO/MDC)“ on page 136)
Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50402 (10.0, “Hardware Statistics
Counters“ on page 53)
December 2005
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Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,
“Ball Signal Descriptions“ on page 14)
Added more text to section 2.7, “JTAG“ on page 28
Clarified counter definitions (10.0, “Hardware Statistics Counters“ on page 53)
Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]
Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and
this bit was mistakenly left in the register definition.
April 2006
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Added Pb-free order code (ZL50402GDG2)
Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)
since it wasn’t really discussed in the DS
Clarified registers UCC, MCC & MCCTH
Renamed register UCC (now PCC), as name was misleading
Updated timing to CPU RvMII, as min. output delay should have been 0 ns
July 2006
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Added typical values to power numbers in “Recommended Operating Conditions” table.
Updated RM6 “CPU_MII_TXEN Output Delay Time” & RM7 “CPU_MII_TXD[3:0] Output Delay Time” max. to
5 ns (old 14 ns)
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