ZL50402GDG datasheet, PDF - EEWORLD Datasheet

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ZL50402GDG: DescriptionLAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208; CategoryWireless rf/communication Telecom circuit; File Size2MB，139 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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ZL50402GDG Overview

LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208

ZL50402GDG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Zarlink Semiconductor (Microsemi)
Objectid	2056617607
package instruction	LBGA,
Reach Compliance Code	compliant
compound_id	219213955
JESD-30 code	S-PBGA-B208
JESD-609 code	e0
length	17 mm
Number of functions	1
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	1.4 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm

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ZL50402

Managed 2FE + 1GE Layer-2

Ethernet Switch

Data Sheet

Zarlink Features

•

Integrated Single-Chip 10/100/1000 Mbps

Ethernet Switch

• Two 10/100 Mbps auto-negotiating Fast

Ethernet (FE) ports with RMII, MII, GPSI,

Reverse MII & Reverse GPSI interface options

• One 10/100/1000 Mbps auto-negotiating port

with GMII & MII interface options, that can be

used as a WAN uplink or as a 9th port

• a 10/100 Mbps Fast Ethernet (FE) CPU port

with Reverse MII interface option

Embedded 2.0 Mbits (256 KBytes) internal

memory for control databases and frame data

buffer

• Supports jumbo frames up to 4 KBytes

CPU access supports the following interface

options:

• 8/16-bit ISA interface

• Serial interface with MII port; recommended

for light management

• Serial interface in lightly managed mode, or in

unmanaged mode with optional I

C EEPROM

interface

Ethernet IEEE 802.3x flow control for full duplex

ports, back pressure flow control for half duplex

ports

8/16-bit

Serial

August 2006

Ordering Information

ZL50402GDG

ZL50402GDG2

208-Ball LBGA

208-Ball LBGA**

**Pb Free Tin/Silver/Copper

-40°C to +85°C

•

Built-in reset logic triggered by system

malfunction

Built-In Self Test for internal SRAM

IEEE-1149.1 (JTAG) test port

•

L2 Switching

•

L2 switching

• MAC address self learning, up to 4 K MAC

addresses

• MAC address table supports unicast and

multicast MAC address and IP multicast

address learning

Supports IP Multicast with IGMP snooping, up to

4 K IP Multicast groups

•

ZL50402

MII

GM II / M II

2-Port 10/100M + 1G

Ethernet Switch

EEPROM

10/100/

1000

PHY

RM II / M II / GPSI

Dual

10/100

PHY

Figure 1 - System Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL50402

January 2005

•

Data Sheet

•

Updated GMII timing (12.4.11, “Gigabit Media Independent Interface (GMII)“ on page 134)

• reduce min. hold time from 1ns to 0.5ns

• reduced max. output delay by 1ns

Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable

June 2005

•

Added 2FE+1GE variant

Corrected ordering code to ZL50402GD”G”

Clarified that port mirroring is only available if the source & destination ports are in RMII mode

Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F

Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap

TSTOUT[0]

Added power sequencing recommendation (1.7, “Power Sequencing“ on page 26)

Added Reverse MII/GPSI timing characteristics (12.4.10, “Reverse General Purpose Serial Interface

(RvGPSI)“ on page 133 and 12.4.12, “MII Management Data Interface (MDIO/MDC)“ on page 136)

Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50402 (10.0, “Hardware Statistics

Counters“ on page 53)

December 2005

•

Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,

“Ball Signal Descriptions“ on page 14)

Added more text to section 2.7, “JTAG“ on page 28

Clarified counter definitions (10.0, “Hardware Statistics Counters“ on page 53)

Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]

Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and

this bit was mistakenly left in the register definition.

April 2006

•

Added Pb-free order code (ZL50402GDG2)

Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)

since it wasn’t really discussed in the DS

Clarified registers UCC, MCC & MCCTH

Renamed register UCC (now PCC), as name was misleading

Updated timing to CPU RvMII, as min. output delay should have been 0 ns

July 2006

•

Added typical values to power numbers in “Recommended Operating Conditions” table.

Updated RM6 “CPU_MII_TXEN Output Delay Time” & RM7 “CPU_MII_TXD[3:0] Output Delay Time” max. to

5 ns (old 14 ns)

Zarlink Semiconductor Inc.

ZL50402GDG Related Products

	ZL50402GDG	ZL50402GDG2
Description	LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208	LAN Switching Circuit, PBGA208, 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
Is it Rohs certified?	incompatible	conform to
Maker	Zarlink Semiconductor (Microsemi)	Zarlink Semiconductor (Microsemi)
package instruction	LBGA,	LBGA,
Reach Compliance Code	compliant	compliant
JESD-30 code	S-PBGA-B208	S-PBGA-B208
JESD-609 code	e0	e1
length	17 mm	17 mm
Number of functions	1	1
Number of terminals	208	208
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	225	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT	LAN SWITCHING CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN LEAD	TIN SILVER COPPER
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	NOT SPECIFIED
width	17 mm	17 mm

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