EEWORLDEEWORLDEEWORLD

Part Number

Search

530WC81M0000DGR

Description
CMOS/TTL Output Clock Oscillator, 81MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530WC81M0000DGR Overview

CMOS/TTL Output Clock Oscillator, 81MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530WC81M0000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency81 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
【Topmicro Smart Display Screen Review】5. Topmicro HMT070ETD-1D Smart Screen Usage Summary
Finally, let 's summarize the use of Topmicro HMT070ETD-1D smart screenTo summarize the functions of Topmicro Smart Screen:RS232 serial communication control display.Note: Default baud rate: 15200 no ...
物联创客 Test/Measurement
The relationship between CPU data bits and bus data bits
Question: If the CPU is 16 bits, does that also require the board bus data bits to be 16 bits?...
04616115 Embedded System
18B20 can't read data, please help
Can you help me look at this program? I need it urgently{:1_110:}...
农逸 Microchip MCU
Collect FPGA xx solution or xx code flow with bitter examples
[size=4][color=#0000ff]It is often said that failure is the mother of success. [/color][/size] [size=4][color=#0000ff]In FPGA project development, it is normal to use solutions and code flows. [/color...
5525 FPGA/CPLD
[Original article] Atmel SAM D21 development board trial experience + various applications to be carried out (updated at any time)
Atmel SAM D21 development board trial experience + various applications to be carried out (updated at any time) The Atmel SAM D21 development board has arrived. Many thanks to eeworld , the administra...
bjwl_6338 MCU
[Repost] The advice given to you by the motherboard repair engineer is quite useful to everyone
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:58[/i][size=5]First of all, let me introduce myself. I work in a notebook manufacturer to repair notebook motherboards. At the most pit...
open82977352 Mobile and portable

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2681  1907  812  2754  1851  54  39  17  56  38 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号