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M7AGL250-FG144

Description
Flash Memory,
Categorystorage    storage   
File Size224KB,12 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

M7AGL250-FG144 Overview

Flash Memory,

M7AGL250-FG144 Parametric

Parameter NameAttribute value
MakerMicrosemi
package instruction,
Reach Compliance Codecompliant
P r o du c t B r i e f
IGLOO
TM
Low Power Flash FPGAs with
Flash*Freeze
TM
Technology
Features and Benefits
Low Power
5 µW Power Consumption in Flash*Freeze Mode
1.2 V or 1.5 V Core Voltage for Low Power
Supports Single-Voltage System Operation
Low Power Active Capability Enables Active FPGA
Operation with Ultra-Low Power (from 25 µW)
Flash*Freeze Technology Enables Ultra-Low Power
Consumption While Maintaining FPGA Content
Quick and Easy Way to Enter and Exit Flash*Freeze
Mode Using Flash*Freeze Pin
30 k to 1 Million System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except AGL030 and ARM
®
-
enabled IGLOO devices) via JTAG (IEEE 1532-
compliant)
FlashLock
®
to Secure FPGA Contents
Architecture Supports Ultra-High Utilization
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/
2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X (except
AGL030), and LVCMOS 2.5 V/5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (AGL250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os (AGL030 only)
Programmable Output Slew Rate (except AGL030) and
Drive Strength
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the IGLOO Family
High Capacity
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL (except
AGL030)
Six CCC Blocks, One with an Integrated PLL
Flexible Phase-Shift, Multiply/Divide, and Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 200 MHz)
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect Ratio 4,608-Bit
RAM Blocks (x1, x2, x4, x9, and x18 organizations
available)
True Dual-Port SRAM (except x18)
In-System Programming (ISP) and Security
Embedded Memory
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
Table 1 •
IGLOO Product Family
IGLOO Devices
ARM-Enabled IGLOO Devices
System Gates
VersaTiles (D-Flip-Flops)
Quiescent Current (typical)
Flash*Freeze Mode (µA)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM Bits
Secure (AES) ISP
1
Integrated PLL in CCCs
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
CS
QFN
VQFP
FBGA
AGL030
30 k
768
in
AGL060
60 k
1,536
Soft ARM7™ Core Support in M7 IGLOO Devices
AGL125
125 k
3,072
AGL250
M7AGL250
250 k
6,144
AGL600
M7AGL600
600 k
13,824
AGL1000
M7AGL1000
1M
24,576
4
1k
6
2
81
8
18
4
1k
Yes
1
18
2
96
CS196
QN132
VQ100
FG144
14
36
8
1k
Yes
1
18
2
133
CS196
QN132
VQ100
FG144
28
36
8
1k
Yes
1
18
4
143
CS196
3
QN132
3
VQ100
FG144
60
108
24
1k
Yes
1
18
4
227
102
144
32
1k
Yes
1
18
4
300
QN132
VQ100
FG144, FG256,
FG484
FG144, FG256,
FG484
Notes:
1. AES is not available for ARM-enabled IGLOO devices.
2. Six chip (main) and three quadrant global networks are available for AGL060 and above.
3. The M7AGL250 device does not support this package.
4. For higher densities and support of additional features, refer to the
IGLOOe Flash FPGAs
datasheet.
January 2007
© 2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.
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