a
Fast, High Voltage Drive, 6-Channel Output
DecDriver
TM
Decimating LCD Panel Driver
AD8381
FUNCTIONAL BLOCK DIAGRAM
10
DB (0:9)
10
10
DAC
VID0
2-STAGE
LATCH
FEATURES
High Voltage Drive:
Rated Settling Time to within 1.3 V of Supply Rails
Output Overload Protection
High Update Rates:
Fast, 100 Ms/s 10-Bit Input Word Rate
Low Power Dissipation: 570 mW
Includes STBY Function
Voltage Controlled Video Reference (Brightness) and
Full-Scale (Contrast) Output Levels
3.3 V or 5 V Logic and 9 V–18 V Analog Supplies
High Accuracy:
Laser Trimming Eliminates External Calibration
Flexible Logic:
INV Reverses Polarity of Video Signal
STSQ/XFR for Parallel AD8381 Operation in
12-Channel Systems
Drives Capacitive Loads:
27 ns Settling Time to 1% into 150 pF Load
Slew Rate 265 V/ s with 150 pF Load
Available in 48-Lead LQFP
APPLICATIONS
LCD Analog Column Driver
PRODUCT DESCRIPTION
10
AD8381
10
STBY
BYP
BIAS
10
2-STAGE
LATCH
10
DAC
VID1
2-STAGE
LATCH
10
DAC
VID2
2-STAGE
LATCH
10
DAC
VID3
E/O
L/R
CLK
STSQ
XFR
10
2-STAGE
LATCH
10
DAC
VID4
10
SEQUENCE
CONTROL
2-STAGE
LATCH
10
DAC
VID5
SCALING
CONTROL
VREFHI
VREFLO
INV
VMID
The AD8381 provides a fast, 10-bit latched decimating digital
input, which drives six high voltage outputs. Ten-bit input
words are sequentially loaded into six separate high-speed, bipolar
DACs. Flexible digital input format allows several AD8381s to be
used in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating and R/L controls the direction of loading as either
Left to Right or Right to Left. Six channels of high voltage
output drivers drive to within 1.3 V of the rail in rated settling
time. The output signal can be adjusted for brightness, signal
inversion and contrast for maximum flexibility.
The AD8381 is fabricated on ADI’s proprietary, fast bipolar
24 V process, providing fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage precision drive
amplifiers on the same chip.
The AD8381 dissipates 570 mW nominal static power. STBY
pin reduces power to a minimum, with fast recovery.
The AD8381 is offered in a 48-lead 7
×
7
×
1.4 mm LQFP
package and operates over the commercial temperature range of
0°C to 85°C.
DecDriver is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD8381–SPECIFICATIONS
Model
VIDEO DC PERFORMANCE
1
VDE
VCME
REFERENCE INPUTS
VMID Range
2
VMID Bias Current
VREFHI
VREFLO
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
VFS Range
3
RESOLUTION
Coding
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
CLK to Data Setup Time: t
1
CLK to STSQ Setup Time: t
3
CLK to XFR Setup Time: t
5
CLK to Data Hold Time: t
2
CLK to STSQ Hold Time: t
4
CLK to XFR Hold Time: t
6
C
IN
I
IH
I
IL
V
IH
V
IL
V
TH
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay
4
: t
7
INV to VID Delay
Output Current
Output Resistance
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
CLK and Data Feedthrough
5
All-Hostile Crosstalk
6
Amplitude
Glitch Duration
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
STBY DVCC Current
OPERATING TEMPERATURE RANGE
(@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, VREFLO = VMID = 7 V, VREFHI = 9.5 V,
T
MIN
= 0 C, T
MAX
= 85 C, unless otherwise noted.)
Min
–7.5
–3.5
6.25
35
VREFLO
VMID – 0.5
Typ
+1.0
+0.5
Max
+7.5
+3.5
9.25
77
AVCC
VREFHI
0.07
165
5.75
Unit
mV
mV
V
µA
V
V
kΩ
µA
µA
V
Bits
100
0
0
0
5
5
5
0.6
0.05
2.0
0.08
3
0.7
0.16
Ms/s
ns
ns
ns
ns
ns
ns
pF
µA
µA
V
V
V
V
ns
ns
mA
Ω
V/µs
V/µs
ns
ns
ns
ns
mV p-p
mV p-p
ns
mV/V
V
mA
V
mA
mA
mA
°C
Conditions
T
MIN
to T
MAX
DAC Code 450 to 800
DAC Code 450 to 800
(VREFHI–VREFLO) = 2.5 V
to VREFLO
20
0.01
125
0
Binary
CLK Rise and Fall Time = 5 ns
NRZ
10
Threshold Voltage
AVCC – VOH, VOL – AGND
50% of VIDx
50% of VIDx
1.4
1
15.5
14
75
29
265
410
27
50
33
55
5
50
45
1.3
17.5
16
13.5
12
30
T
MIN
to T
MAX
, V
O
= 5 V Step, C
L
= 150 pF
32
75
40
100
AVCCx = +15.5 V
±
1 V
3
0.6
18
9
33
1.8
0.03
0
5.5
25
18
40
3
0.1
85
STBY = H
STBY = H
NOTES
1
VDE = Differential Error Voltage. VCME = Common-Mode Error Voltage. See the Functional Description section.
2
See Figure 6 in the Functional Description section.
3
VFS = 2
×
(VREFHI–VREFLO). See Functional Description section.
4
Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5
Measured on one output as CLK is driven and STSQ and XFR are held LOW.
6
Measured on one output as the other five are changing from 000
HEX
to 3FF
HEX
for both states of INV.
Specifications subject to change without notice.
–2–
REV. 0
AD8381
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
CLK to Data Setup Time
CLK to Data Hold Time
CLK to STSQ Setup Time
CLK to STSQ Hold Time
CLK to XFR Setup Time
CLK to XFR Hold Time
CLK to VID Delay
Conditions
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
Min
0
5
0
5
0
5
13.5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
15.5
17.5
DB (0:9)
–1
0
t
1
CLK
t
2
t
3,
t
5
STSQ, XFR
t
4,
t
6
Figure 1. Timing Requirement E/O = HIGH
DB (0:9)
–1
0
t
1
CLK
t
2
t
3
STSQ
t
4
t
5
XFR
t
6
Figure 2. Timing Requirements E/O = LOW
CLK
XFR
t
7
VIDx
Figure 3. Output Timing
REV. 0
–3–
AD8381
ABSOLUTE MAXIMUM RATINGS
1
MAXIMUM POWER DISSIPATION
Supply Voltages
AVCCx – AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
DVCC – DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Voltages
Maximum Digital Input Voltages . . . . . . . . DVCC + 0.5 V
Minimum Digital Input Voltages . . . . . . . . DGND – 0.5 V
Maximum Analog Input Voltages . . . . . . . . . AVCC + 0.5 V
Minimum Analog Input Voltages . . . . . . . . AGND – 0.5 V
Internal Power Dissipation
2
LQFP Package @ 25°C Ambient . . . . . . . . . . . . . . . . 2.7 W
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Infinite
Operating Temperature Range . . . . . . . . . . . . . . 0°C to 85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
NOTES
1
Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to the absolute
maximum ratings for extended periods may reduce device reliability.
2
48-lead LQFP Package:
θ
JA
= 45°C/W (Still Air, 4-Layer PCB)
θ
JC
= 19°C/W
The maximum power that can be safely dissipated by the AD8381
is limited by its junction temperature. The maximum safe junc-
tion temperature for plastic encapsulated devices is determined
by the glass transition temperature of the plastic, approximately
150°C. Exceeding this limit temporarily may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
To ensure proper operation within the specified operating tem-
perature range, it is necessary to limit the maximum power
dissipation as follows:
P
DMAX
= (T
JMAX
–
T
A
)/θ
JA
where
T
JMAX
= 150°C.
3.5
MAXIMUM POWER DISSIPATION – W
3.0
2.5
Overload Protection
The AD8381 employs a two-stage overload protection circuit
that consists of an output current limiter and a thermal shutdown.
The maximum current at any one output of the AD8381 is
internally limited to 100 mA average. In the event of a momen-
tary short-circuit between a video output and a power supply rail
(VCC or AGND), the output current limit is sufficiently low to
provide temporary protection.
The thermal shutdown “debiases” the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short-circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ with a period determined by
the thermal time constant and the hysteresis of the thermal trip
point. The thermal shutdown provides long term protection by
limiting the average junction temperature to a safe level.
Recovery from a momentary short-circuit is fast, approximately
100 ns. Recovery from a thermal shutdown is slow and is
dependent on the ambient temperature.
2.0
1.5
1.0
0.5
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE – C
80
90
Figure 4. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature
Range
Package
Description
48-Lead LQFP
Package
Option
ST-48
AD8381AST
0°C to 85°C
AD8381AST-REEL
Reel
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8381 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD8381
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
No Connect
Data Input
Even/Odd Select
10-Bit Data Input MSB = DB (9).
The active CLK edge is the rising edge when this input is held HIGH
and it is the falling edge when this input is held LOW.
Data is loaded sequentially on the rising edges of CLK when this input
is HIGH and loaded on the falling edges when this input is LOW.
A new data loading sequence begins on the left, with Channel 0, when this
input is LOW, and on the right, with Channel 5 when this input is HIGH.
When this pin is HIGH, the analog output voltages are above VMID.
When LOW, the analog output voltages are below VMID.
This pin is normally connected to the analog ground plane.
Digital Power Supply.
Analog Power Supplies.
When HIGH, the internal circuits are “debiased” and the power
dissipation drops to a minimum.
A 0.1
µF
capacitor connected between this pin and AGND ensures
optimum settling time.
These pins are normally connected to the analog ground plane.
These pins are directly connected to the analog inputs of the LCD panel.
The voltage applied between this pin and AGND sets the midpoint
reference of the analog outputs. This pin is normally connected to VCOM.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
A new data loading sequence begins on the rising edge of CLK when
this input was HIGH on the preceding rising edge of CLK and the E/O
input is held HIGH.
A new data loading sequence begins on the falling edge of CLK when
this input was HIGH on the preceding falling edge of CLK and the E/O
input is held LOW.
Data is transferred to the outputs on the immediately following falling
edge of CLK when this input is HIGH on the rising edge of CLK.
Clock Input.
Description
1, 12, 19, 23, NC
24, 43–45
2–11
DB (0:9)
13
E/O
14
15
16
17
18, 27, 31,
35, 42
20
21
22, 25, 29,
33, 37, 41
26, 28, 30,
32, 34, 36
38
39
40
46
R/L
INV
DGND
DVCC
AVCCx
STBY
BYP
AGNDx
VID5, VID4, VID3,
VID2, VID1, VID0
VMID
VREFLO
VREFHI
STSQ
Right/Left Select
Invert
Digital Supply Return
Digital Power Supply
Analog Power Supplies
Standby
Bypass
Analog Supply Returns
Analog Outputs
Midpoint Reference
Full-Scale Reference
Full-Scale Reference
Start Sequence
47
48
XFR
CLK
Data Transfer
Clock
PIN CONFIGURATION
AVCCDAC
AGNDDAC
VREFHI
VREFLO
48 47 46 45 44 43 42 41 40 39 38 37
NC
1
DB0
2
DB1
3
DB2
DB3
5
DB4
6
DB5
7
4
VMID
AGND0
36
VID0
35
AVCC0, 1
34
VID1
33
AGND1, 2
32
VID2
31
AVCC2, 3
30
VID3
29
AGND3, 4
28
VID4
27
AVCC4, 5
26
VID5
25
AGND5
STSQ
NC
CLK
XFR
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
DB6
8
DB7
9
DB8
10
DB9
11
NC
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
AD8381
AGNDBIAS
NC
R/L
DGND
E/O
INV
DVCC
AVCCBIAS
NC
STBY
NC = NO CONNECT
REV. 0
–5–
BYP
NC
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