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FEATURES
14-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 71 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
PRODUCT DESCRIPTION
14-Bit, 300 MSPS
High Speed TxDAC+
®
D/A Converter
AD9755
*
FUNCTIONAL BLOCK DIAGRAM
DVDD
DCOM
AVDD
ACOM
PORT1
LATCH
MUX
PORT2
LATCH
DAC LATCH
I
OUTA
DAC
I
OUTB
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
PLL
CLOCK
MULTIPLIER
REFERENCE
REFIO
FSADJ
AD9755
RESET LPF DIV0 DIV1 PLLLOCK
The AD9755 is a dual, muxed port, ultrahigh speed, single-
channel, 14-bit CMOS DAC. It integrates a high quality 14-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9755 offers excep-
tional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9755 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differentially
or single-ended, with a signal swing as low as 1 V p-p.
The DAC utilizes a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and maximize dynamic accuracy. Differential current
outputs support single-ended or differential applications. The
differential outputs each provide a nominal full-scale current
from 2 mA to 20 mA.
The AD9755 is manufactured on an advanced low cost 0.35
µm
CMOS process. It operates from a single supply of 3.0 V to 3.6 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9755 is a member of a pin compatible family of high
speed TxDAC+s providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh Speed 300 MSPS Conversion Rate.
3. Dual 14-Bit Latched, Multiplexed Input Ports. The AD9755
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9755 includes a 1.20 V
temperature compensated band gap voltage reference.
*Protected
by U.S. Patent numbers 5450084, 5568145, 5689257, and 5703519.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9755–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
PLLVDD
CLKVDD
Analog Supply Current (I
AVDD
)
4
Digital Supply Current (I
DVDD
)
4
PLL Supply Current (I
PLLVDD
)
4
Clock Supply Current (I
CLKVDD
)
4
Power Dissipation
4
(3 V, I
OUTFS
= 20 mA)
Power Dissipation
5
(3 V, I
OUTFS
= 20 mA)
Power Supply Rejection Ratio
6
—AVDD
Power Supply Rejection Ratio
6
—DVDD
OPERATING RANGE
NOTES
1
Measured at I
OUTA
, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32× the I
REF
current.
3
An external buffer amplifier is recommended to drive any external load.
4
100 MSPS f
DAC
with PLL on, f
OUT
= 100 MHz, all supplies = 3.0 V.
5
300 MSPS f
DAC
.
6
±
5% power supply variation.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless
otherwise noted.)
Min
14
–5
–3
–0.025
–2
–2
2.0
–1.0
±
2.5
±
1.5
±
0.01
±
0.5
±
0.25
100
5
1.14
1.20
100
1.26
+5
+3
+0.025
+2
+2
20.0
+1.25
Typ
Max
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
MΩ
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
0.1
1
0
±
50
±
100
±
50
1.25
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
33
3.5
4.5
10.0
155
216
3.6
3.6
3.6
3.6
36
4.5
5.1
11.5
165
+1
+0.04
+85
–1
–0.04
–40
V
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
–2–
REV. B
AD9755
DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
DAC
)
Output Settling Time (t
ST
) (to 0.1%)
1
Output Propagation Delay (t
PD
)
1
Glitch Impulse
1
Output Rise Time (10% to 90%)
1
Output Fall Time (90% to 10%)
1
Output Noise (I
OUTFS
= 20 mA)
Output Noise (I
OUTFS
= 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
DAC
= 100 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
f
DATA
= 65 MSPS; f
OUT
= 1.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 5.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 10.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 20.1 MHz
2
f
DATA
= 65 MSPS; f
OUT
= 30.1 MHz
2
f
DAC
= 160 MSPS; f
OUT
= 1.1 MHz
f
DAC
= 160 MSPS; f
OUT
= 11.1 MHz
f
DAC
= 160 MSPS; f
OUT
= 31.1 MHz
f
DAC
= 160 MSPS; f
OUT
= 51.1 MHz
f
DAC
= 160 MSPS; f
OUT
= 71.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 1.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 26.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 51.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 101.1 MHz
f
DAC
= 300 MSPS; f
OUT
= 141.1 MHz
Spurious-Free Dynamic Range within a Window
f
DAC
= 100 MSPS; f
OUT
= 1 MHz; 2 MHz Span
0 dBFS Output
f
DAC
= 65 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
f
DAC
= 150 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
f
DAC
= 100 MSPS; f
OUT
= 1.00 MHz
T
A
= 25°C
T
MIN
to T
MAX
f
DAC
= 65 MHz; f
OUT
= 2.00 MHz
f
DAC
= 160 MHz; f
OUT
= 2.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
f
DAC
= 65 MSPS; f
OUT
= 2.00 MHz to 2.77 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
NOTES
1
Measured single-ended into 50
Ω
load.
2
Single Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1).
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA,
Differential Transformer-Coupled Output, 50 Doubly Terminated, unless otherwise noted.)
Min
300
11
1
5
2.5
2.5
50
30
Typ
Max
Unit
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
74
84
77
79
79
79
78
74
70
80
77
72
72
69
80
71
67
61
60
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
83.5
93
85
85
dBc
dBc
dBc
–83
–83
–78
–78
–73
–71
dBc
dBc
dBc
dBc
75
73
70
dBc
dBc
dBc
REV. B
–3–
AD9755
DIGITAL SPECIFICATIONS
Parameter
DIGITAL INPUTS
Logic 1
Logic 0
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
S
), T
A
= 25°C
Input Hold Time (t
H
), T
A
= 25°C
Latch Pulsewidth (t
LPW
), T
A
= 25°C
Input Setup Time (t
S,
PLLVDD = 0 V), T
A
= 25°C
Input Hold Time (t
H,
PLLVDD = 0 V), T
A
= 25°C
CLK to PLLLOCK Delay (t
D
, PLLVDD = 0 V), T
A
= 25°C
Latch Pulsewidth (t
LPW
PLLVDD = 0 V), T
A
= 25°C
PLLOCK (V
OH
)
PLLOCK (V
OL
)
CLK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
Min CLK Frequency*
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
Min
2.1
–10
–10
1.0
1.0
1.5
–1.0
2.5
3.5
1.5
3.0
5
0.5
0.5
–1.5
1.7
4.0
Typ
3
0
Max
Unit
V
V
µA
µA
pF
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
MHz
0.9
+10
+10
0.3
0
0.75
0.5
3
2.25
1.5
1.5
6.25
*Min
CLK Frequency only applies when using internal PLL. When PLL is disabled, there is no minimum CLK frequency.
–4–
REV. B
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