ATtiny828
8-bit AVR Microcontroller with 8K Bytes In-System
Programmable Flash
DATASHEET SUMMARY
Features
High Performance, Low Power Atmel
®
AVR
®
8-bit Microcontroller
Advanced RISC Architecture
123 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20 MHz
Non-volatile Program and Data Memories
8K Bytes of In-System Programmable Flash Program Memory
Endurance: 10,000 Write/Erase Cycles
256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
512 Bytes Internal SRAM
Optional Boot Code Section with Independent Lock Bits
Data Retention: 20 Years at 85
o
C / 100 Years at 25
o
C
Peripheral Features
One 8-bit and one 16-bit Timer/Counter with Two PWM Channels, Each
Programmable Ultra Low Power Watchdog Timer
On-chip Analog Comparator
10-bit Analog to Digital Converter
28 External and 4 Internal, Single-ended Input Channels
Full Duplex USART with Start Frame Detection
Master/Slave SPI Serial Interface
Slave I
2
C Serial Interface
Special Microcontroller Features
Low Power Idle, ADC Noise Reduction, and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit with Supply Voltage Sampling
External and Internal Interrupt Sources
Pin Change Interrupt on 28 Pins
Calibrated 8MHz Oscillator with Temperature Calibration Option
Calibrated 32kHz Ultra Low Power Oscillator
High-Current Drive Capability on 8 I/O Pins
I/O and Packages
32-lead TQFP, and 32-pad QFN/MLF: 28 Programmable I/O Lines
Speed Grade
0 – 2 MHz @ 1.7 – 1.8V
0 – 4 MHz @ 1.8 – 5.5V
0 – 10 MHz @ 2.7 – 5.5V
0 – 20 MHz @ 4.5 – 5.5V
8371AS–AVR–08/12
Low Power Consumption
Active Mode: 0.2 mA at 1.8V and 1MHz
Idle Mode: 30 µA at 1.8V and 1MHz
Power-Down Mode (WDT Enabled): 1 µA at 1.8V
Power-Down Mode (WDT Disabled): 100 nA at 1.8V
1.
Pin Configurations
Figure 1.
ATtiny828 Pinout in MLF32.
PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO)
PC0 (PCINT16/ADC16/TOCC0/SS/XCK)
PD3 (PCINT27/ADC27/SCL/SCK)
PD2 (PCINT26/ADC26/RESET/DW)
PD1 (PCINT25/ADC25/MISO)
PD0 (PCINT24/ADC24/SDA/MOSI)
PB7 (PCINT15/ADC15)
PB6 (PCINT14/ADC14)
32
31
30
29
28
27
26
25
(PCINT18/ADC18/TOCC2/RXD/INT1) PC2
(PCINT19/ADC19/TOCC3/TXD) PC3
(PCINT20/ADC20/TOCC4) PC4
VCC
GND
(PCINT21/ADC21/TOCC5/ICP1/T0) PC5
(PCINT22/ADC22/CLKI/TOCC6) PC6
(PCINT23/ADC23/TOCC7/T1) PC7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
PB5 (PCINT13/ADC13)
PB4 (PCINT12/ADC12)
PB3 (PCINT11/ADC11)
GND
PB2 (PCINT10/ADC10)
PB1 (PCINT9/ADC9)
AVCC
PB0 (PCINT8/ADC8)
NOTE: Bottom pad should be
soldered to ground
Figure 2.
ATtiny828 Pinout in TQFP32.
PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO)
PC0 (PCINT16/ADC16/TOCC0/SS/XCK)
PD3 (PCINT27/ADC27/SCL/SCK)
PD2 (PCINT26/ADC26/RESET/DW)
PD1 (PCINT25/ADC25/MISO)
PD0 (PCINT24/ADC24/SDA/MOSI)
PB7 (PCINT15/ADC15)
PB6 (PCINT14/ADC14)
32
31
30
29
28
27
26
25
(PCINT18/ADC18/TOCC2/RXD/INT1) PC2
(PCINT19/ADC19/TOCC3/TXD) PC3
(PCINT20/ADC20/TOCC4) PC4
VCC
GND
(PCINT21/ADC21/TOCC5/ICP1/T0) PC5
(PCINT22/ADC22/CLKI/TOCC6) PC6
(PCINT23/ADC23/TOCC7/T1) PC7
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
(PCINT0/ADC0) P
A0
(PCINT1/ADC1/AIN0) P
A1
(PCINT2/ADC2/AIN1) P
A2
(PCINT3/ADC3) P
A3
(PCINT4/ADC4) P
A4
(PCINT5/ADC5) P
A5
(PCINT6/ADC6) P
A6
(PCINT7/ADC7) P
A7
1
2
3
4
5
6
7
8
PB5 (PCINT13/ADC13)
PB4 (PCINT12/ADC12)
PB3 (PCINT11/ADC11)
GND
PB2 (PCINT10/ADC10)
PB1 (PCINT9/ADC9)
AVCC
PB0 (PCINT8/ADC8)
(PCINT0/ADC0) P
A0
(PCINT1/ADC1/AIN0) P
A1
(PCINT2/ADC2/AIN1) P
A2
(PCINT3/ADC3) P
A3
(PCINT4/ADC4) P
A4
(PCINT5/ADC5) P
A5
(PCINT6/ADC6) P
A6
(PCINT7/ADC7) P
A7
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
2
1.1
1.1.1
Pin Description
VCC
Supply voltage.
1.1.2
AVCC
AV
CC
is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected
to V
CC
even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to V
CC
through a low-pass
filter, as described in
“Noise Canceling Techniques” on page 145.
All pins of Port A and Port B are powered by AV
CC
. All other I/O pins take their supply voltage from V
CC
.
1.1.3
GND
Ground.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in
Table 107 on page 250.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.5
Port A (PA7:PA0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. See
Table 107 on page 250
for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, the analog comparator, and ADC. See
“Alternative Port
Functions” on page 63.
1.1.6
Port B (PB7:PB0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. See
Table 103 on page 247
for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, and ADC. See
“Alternative Port Functions” on page 63.
1.1.7
Port C (PC7:PC0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. Optionally, extra high sink capability can be enabled. See
Table 103 on page 247
for port
drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, ADC, timer/counter, external interrupts, and serial
interfaces. See
“Alternative Port Functions” on page 63.
1.1.8
Port D (PD3:PD0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers of PD0 and PD3
have symmetrical drive characteristics, with both sink and source capability. Output buffer PD1 has high sink and
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
3
standard source capability, while PD2 only has weak drive characteristics due to its use as a reset pin. See
Table 103 on
page 247
for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, ADC, serial interfaces, and debugWire. See
“Alternative
Port Functions” on page 63.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
4
2.
Overview
ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 3.
V
CC
Block Diagram
RESET
GND
POWER
SUPERVISION:
POR
BOD
RESET
ON-CHIP
DEBUGGER
EEPROM
ISP
INTERFACE
DEBUG
INTERFACE
CALIBRATED ULP
OSCILLATOR
CALIBRATED
OSCILLATOR
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
WATCHDOG
TIMER
TIMING AND
CONTROL
TWO-WIRE
INTERFACE
USART
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
TEMPERATURE
SENSOR
ANALOG
COMPARATOR
MULTIPLEXER
CPU CORE
8-BIT DATA BUS
VOLTAGE
REFERENCE
ADC
PORT A
PORT B
PORT C
PORT D
PA[7:0]
PB[7:0]
PC[7:0]
PD[3:0]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
5
京公网安备 11010802033920号
EEWORLD
