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N80C251TB24

Description
TQHIGH-PERFORMANCE CHMOS MICROCONTROLLER
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size166KB,36 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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N80C251TB24 Overview

TQHIGH-PERFORMANCE CHMOS MICROCONTROLLER

N80C251TB24 Parametric

Parameter NameAttribute value
MakerIntel
Parts packaging codeLCC
package instructionQCCJ, LDCC44,.7SQ
Contacts44
Reach Compliance Codeunknow
Has ADCNO
Address bus width18
bit size8
CPU series80251
maximum clock frequency24 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeS-PQCC-J44
length16.5862 mm
Number of I/O lines32
Number of terminals44
Maximum operating temperature70 °C
Minimum operating temperature
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC44,.7SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply5 V
Certification statusNot Qualified
RAM (bytes)1024
rom(word)0
Maximum seat height4.57 mm
speed24 MHz
Maximum slew rate83 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width16.5862 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
8xC251TB/TQ
HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Commercial/Express
Real-time and Programmed Wait State
User-selectable Configurations:
Bus Operation
Binary-code Compatible with
MCS
®
51
Pin Compatible with 44-pin PLCC and
40-pin PDIP MCS 51 Sockets
Register-based MCS
®
251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Double Words
Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and
Logic Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
Linear Addressing
256-Kbyte Expanded External
— External Wait States (0-3 wait
states)
— Address Range & Memory Mapping
— Page Mode
— Extended Data Float Timings or
8xC251Sx Compatible AC Timings
32 Programmable I/O Lines
Eight Maskable Interrupt Sources with
Four Programmable Priority Levels
Three Flexible 16-bit Timer/counters
Hardware Watchdog Timer
Programmable Counter Array
Code/Data Memory Space
ROM Options:
16 Kbytes or without ROM
16-bit Internal Code Fetch
64-Kbyte Extended Stack Space
On-chip Data RAM Options:
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
Two Programmable Serial I/O Ports
— Framing Error Detection
— Automatic Address Recognition
High-performance CHMOS Technology
Static Standby to 24-MHz Operation
Complete System Development
512-Byte
8-bit, 2-clock External Code Fetch in
Page Mode
Fast MCS 251 Instruction Pipeline
Support
— Compatible with Existing Tools
— MCS 251 Tools Available: Compiler,
Assembler, Debugger, ICE
Package Options (PDIP and PLCC)
© INTEL CORPORATION
December 2003
Order Number:
273129-002

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