UPD4442162GF-A60Y datasheet, PDF

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UPD4442162GF-A60Y: DescriptionCache SRAM, 256KX16, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100; Categorystorage storage; File Size223KB，28 Pages; ManufacturerNEC Electronics

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UPD4442162GF-A60Y Overview

Cache SRAM, 256KX16, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

UPD4442162GF-A60Y Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4194304 bit
Memory IC Type	CACHE SRAM
memory width	16
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4442162-Y, 4442182-Y, 4442322-Y, 4442362-Y

4M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

SINGLE CYCLE DESELECT

Description

The

PD4442162-Y is a 262,144-word by 16-bit, the

PD4442182-Y is a 262,144-word by 18-bit,

PD4442322-Y is

a 131,072-word by 32-bit and the

PD4442362-Y is a 131,072-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using Full-CMOS six-transistor memory cell.

The

PD4442162-Y,

PD4442182-Y,

PD4442322-Y and

PD4442362-Y integrates unique synchronous peripheral

circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive

edge of the single clock input (CLK).

The

PD4442162-Y,

PD4442182-Y,

PD4442322-Y and

PD4442362-Y are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer

memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

PD4442162-Y,

PD4442182-Y,

PD4442322-Y and

PD4442362-Y are packaged in 100-pin PLASTIC LQFP

with a 1.4 mm package thickness for high density and low capacitive loading.

Features

•

3.3 V (A version) or 2.5 V (C version) Core Supply

•

Synchronous operation

•

Extended operating temperature (T

= –40 to +85

°C)

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

Single-Cycle deselect timing

•

All registers triggered off positive clock edge

•

3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.5 ns (250 MHz), 2.8 ns (225 MHz), 3.0 ns (200 MHz), 3.5 ns (167 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 - /BW4 (

PD4442322-Y,

PD4442362-Y), /BW1 - /BW2 (

PD4442162-Y,

PD4442182-Y), /BWE

Global write enable : /GW

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15503EJ2V0DS00 (2nd edition)

Date Published May 2001 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

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