STK10C48
2K x 8 nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
•
STORE
to EEPROM Initiated by Hardware
•
RECALL
to SRAM Initiated by Hardware or
Power Restore
• Automatic
STORE
Timing
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 28-Pin 300 mil PDIP, 300 mil SOIC and
350 mil SOIC Packages
DESCRIPTION
The Simtek STK10C48 is a fast static
RAM
with a non-
volatile electrically erasable
PROM
(
EEPROM
) element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of times,
while independent nonvolatile data resides in
EEPROM
. Data may easily be transferred from the
SRAM
to the
EEPROM
(the
STORE
operation), or from
the
EEPROM
to the
SRAM
(the
RECALL
operation),
using the NE pin. Transfers from the
EEPROM
to the
SRAM
(the
RECALL
operation) also take place auto-
matically on restoration of power. The STK10C48
combines the high performance and ease of use of a
fast
SRAM
with nonvolatile data integrity.
The STK10C48 features industry-standard pinout for
nonvolatile
RAM
s.
BLOCK DIAGRAM
EEPROM ARRAY
32 x 512
ROW DECODER
PIN CONFIGURATIONS
NE
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
STORE
STATIC RAM
ARRAY
32 x 512
RECALL
V
CC
W
NC
A
8
A
9
NC
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
PIN NAMES
STORE/
RECALL
CONTROL
A
0
- A
10
W
DQ
0
- DQ
7
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Nonvolatile Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
E
G
NE
E
W
G
NE
V
CC
V
SS
July 1999
3-1
STK10C48
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC
c
(V
CC
= 5.0V
±
10%)
b
INDUSTRIAL
UNITS
MIN
MAX
95
85
75
65
3
10
30
25
21
18
750
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
–40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
MIN
MAX
N/A
90
75
65
3
10
N/A
26
22
19
750
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
V
V
V
V
°C
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
t
AVAV
= 20ns, E
≥
V
IH
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
NOTES
PARAMETER
Average V
CC
Current
1
I
CC
I
CC
I
SB
d
2
c
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
3
e
1
I
SB
e
2
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b:
Note c:
Note d:
Note e:
The STK10C48-20 requires V
CC
= 5.0V
±
5% supply to operate at specified speed.
I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
I
CC
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
E
≥
2
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
CAPACITANCE
f
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
8
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note f:
These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
July 1999
3-2
STK10C48
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAV
g
t
AVQV
h
t
GLQV
t
AXQX
h
t
ELQX
t
EHQZ
i
t
GLQX
t
GHQZ
i
t
ELICCH
f
t
EHICCL
e, f
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
7
0
25
5
5
7
0
10
0
35
20
22
8
5
5
10
0
13
0
45
MIN
MAX
20
25
25
10
5
5
13
0
15
MIN
MAX
25
35
35
15
5
5
15
MIN
MAX
35
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK10C48-20
STK10C48-25
(V
CC
= 5.0V
±
10%)
b
STK10C48-35
STK10C48-45
UNITS
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note h: I/O state assumes E, G < V
IL
, W > V
IH
, and NE
≥
V
IH
; device is continuously selected.
Note i: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g, h
t
AVAV
ADDRESS
5
3
2
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
g
t
AVAV
ADDRESS
t
ELQV
E
t
ELQX
t
EHQZ
7
6
1
2
t
EHICCL
1
1
G
4
t
GLQV
t
GHQZ
9
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
10
DATA VALID
8
ACTIVE
July 1999
3-3
STK10C48
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
i, j
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
20
15
15
8
0
15
0
0
7
5
MAX
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK10C48-20
STK10C48-25
(V
CC
= 5.0V
±
10%)
b
STK10C48-35
STK10C48-45
UNITS
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥
V
IH
during address transitions. NE
≥
V
IH
.
SRAM WRITE CYCLE #1:
W Controlled
k
t
AVAV
ADDRESS
t
ELWH
E
14
19
12
t
WHAX
t
AVWH
t
AVWL
W
t
WLWH
15
13
18
17
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
20
DATA VALID
16
t
WHDX
t
WHQX
21
SRAM WRITE CYCLE #2:
E Controlled
k
t
AVAV
ADDRESS
t
AVEL
E
18
14
19
12
t
ELEH
t
EHAX
t
AVEH
W
t
WLEH
16
13
17
t
DVEH
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
15
t
EHDX
July 1999
3-4
STK10C48
MODE SELECTION
E
H
L
L
L
L
L
L
W
X
H
L
H
L
L
H
G
X
L
X
L
H
L
H
NE
X
H
H
L
L
L
X
MODE
Not Selected
Read SRAM
Write SRAM
Nonvolatile
RECALL
l
Nonvolatile
STORE
No Operation
POWER
Standby
Active
Active
Active
I
CC2
Active
Note l:
An automatic
RECALL
takes place at power up, starting when V
CC
exceeds 4.25V and taking t
RESTORE
.
STORE
CYCLES #1 & #2
SYMBOLS
NO.
#1
22
23
24
25
26
27
28
t
NLWL
t
ELWL
t
WLEL
t
WLQXm
t
WLNHn
#2
t
ELQX
t
ELNH
Alt.
t
STORE
t
WC
STORE
Cycle Time
STORE
Initiation Cycle Time
Output Disable Set-up to NE Fall
t
GHEL
t
NLEL
Output Disable Set-up to E Fall
NE Set-up
Chip Enable Set-up
Write Enable Set-up
PARAMETER
(V
CC
= 5.0V
±
10%)
b
MIN
MAX
10
20
5
5
5
5
5
UNITS
ms
ns
ns
ns
ns
ns
ns
t
GHNL
Note m: Measured with W and NE both returned high, and G returned low.
STORE
cycles are inhibited below 4.0V.
Note n: Once t
WC
has been satisfied by NE, G, W and E, the
STORE
cycle is completed automatically. Any of NE, G, W or E may be used to terminate
the
STORE
initiation cycle.
Note o: If E is low for any period of time in which W is high while G and NE are low, then a
RECALL
cycle may be initiated.
STORE
CYCLE #1:
W Controlled
o
NE
G
W
24
t
GHNL
26
t
NLWL
23
t
WLNH
E
27
t
ELWL
HIGH IMPEDANCE
22
t
WLQX
DQ (DATA OUT)
STORE
CYCLE #2:
E Controlled
o
NE
26
t
NLEL
25
t
GHEL
G
W
E
28
t
WLEL
23
t
ELNH
HIGH IMPEDANCE
22
t
ELQX
DQ (DATA OUT)
July 1999
3-5
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