Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (TQFN) (soldering, 10s) ...................+300°C
Soldering Temperature (reflow) ......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
24 TQFN
Junction-to-Ambient Thermal Resistance (B
JA
) .........65.1°C/W
Junction-to-Case Thermal Resistance (B
JC
) ................5.4°C/W
25 WLP
Junction-to-Ambient Thermal Resistance (B
JA
) ...........52°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
Operating Supply Voltage
Second Logic Supply
SYMBOL
V
CC
V
LA
I
CC
All key switches open, oscillator
running
N keys pressed
Sleep-Mode Supply Current
POR Threshold
KEY-SWITCH SPECIFICATIONS
Key-Switch Source Current
Key-Switch Source Voltage
Key-Switch Resistance
Startup Time from Sleep
GPIO SPECIFICATIONS
External Supply Voltage
COL7–COL4 (LED Drivers)
LED Port-to-Port Sink Current Variation
V
LED
V
CC
= 3.3V, V
OL
= 1V, T
A
= +25NC,
10mA output mode
Q1.5
5
Q2.4
V
%
I
KEY
V
KEY
R
KEY
t
START
(Note 4)
2
28
0.45
40
0.5
5
2.7
FA
V
kI
ms
I
SL
V
POR
Not using GPO or LED configuration
CONDITIONS
MIN
1.62
V
CC
TYP
3.3
3.3
50
50 + 28
O
N
1.8
1.2
3
FA
V
MAX
3.6
3.6
65
FA
UNITS
V
V
Operating Supply Current
Maxim Integrated
2
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I
2
C Interface and High Level of ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
10mA Port Sink Current
COL7–COL4
SYMBOL
V
OL
= 1V
I
OL
V
OL
= 0.5V
V
OL
= 1V
I
OL
V
OL
= 0.5V
V
IH
V
IL
I
LEAKAGE
I
LEAKAGE
C
IN
N keys pressed simultaneously
V
OL
V
CC
= 1.62V and I
SINK
= 2.5mA
V
CC
= 1.62V and I
SINK
= 5mA
V
CC
= 1.62V and I
SOURCE
= 2.5mA
V
OH
V
CC
= 1.62V and I
SOURCE
= 5mA
V
OL
f
PWM
V
IH
V
IL
I
LEAKAGE
V
OL
C
IN
Input voltage = 5.5V or V
GND
I
SINK
= 6mA
(Notes 4, 5)
-1
I
SINK
= 6mA
Derived from oscillator clock
500
V
CC
-
120
V
CC
-
250
CONDITIONS
T
A
= +25NC
V
CC
= 3.3V
V
CC
= 3.6V,
T
A
= +25NC
T
A
= +25NC
V
CC
= 3.3V
V
CC
= 3.6V,
T
A
= +25NC
0.7
O
V
S
0.3
O
V
S
-2
-1
20
500
50
80
V
CC
-
40
V
CC
-
70
0.6
100
250
+2
+1
18.13
18.47
20
19.05
V
V
FA
FA
pF
pF
mV
MIN
8.6
9.04
10
9.5
21.52
21.34
mA
TYP
MAX
11.4
10.96
mA
UNITS
20mA Port Sink Current
COL7–COL4
Input High Voltage
COL_, ROW_
Input Low Voltage
COL_, ROW_
Input Leakage Current
COL3–COL0, ROW_
Input Leakage Current
COL7–COL4
Input Capacitance
COL_, ROW_
Maximum Allowable Load Capacitance
for Keyscan Function
Output Low Voltage
COL_, ROW_
Output High Voltage
COL3–COL0, ROW_
Output Logic-Low Voltage
(INT)
PWM Frequency
SERIAL-INTERFACE SPECIFICATIONS
Input High Voltage
SDA, SCL, AD0
Input Low Voltage
SDA, SCL, AD0
Input Leakage Current
SDA, SCL, AD0
Output Logic-Low Voltage
SDA
Input Capacitance
SDA, SCL, AD0
Maxim Integrated
V
S
= V
CC
or V
LA
depending on
reference logic level setting
Input voltage = V
CC
or V
GND
Input voltage = 5V
mV
V
Hz
0.7
O
V
CC
0.3
O
V
CC
+1
0.6
10
V
V
FA
V
pF
3
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I
2
C Interface and High Level of ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
I
2
C
TIMING SPECIFICATIONS
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F, TX
t
SP
C
B
t
TIMEOUT
IEC 61000-4-2 Air-Gap Discharge
ROW7–ROW0, COL7–COL0
IEC 61000-4-2 Contact Discharge
All Other Pins
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
Human Body Model
Q8
Q2.5
kV
(Notes 4, 5)
(Notes 4, 5)
(Notes 4, 7)
(Notes 4, 8)
(Note 4)
14
19
(Note 6)
100
1.3
0.7
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
300
300
250
50
400
27
Bus timeout enabled
Bus timeout disabled
0.05
0
1.3
0.6
0.6
0.6
0.9
400
400
kHz
Fs
Fs
Fs
Fs
Fs
ns
Fs
Fs
ns
ns
ns
ns
pF
ms
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Serial-Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL Signals,
Receiving
Fall Time of SDA Signal, Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
Bus Time Out
ESD PROTECTION
Q15
kV
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
All digital inputs at V
CC
or GND.
Guaranteed by design.
C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7:
I
SINK
= 6mA. C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
Note 8:
Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
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