DS3816C-512
16Mb Advanced NV SRAM with Clock
www.maxim-ic.com
FEATURES
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5V operation ±10%
Surface-mount NV RAM BGA module
construction
512k x 32 NV SRAM memory space and
separate 64 x 8 real-time clock memory
space
Real-time clock maintains hundredths of
seconds, seconds, minutes, hours, day, date,
month and year with leap year compensation
valid up to 2100
Removable backup power source provides
more than 8 years of timekeeping and data
retention
Read and write access times as fast as 70ns
for NV SRAM memory and 150ns for
real-time clock
Automatic data protection during power loss
Unlimited write cycle endurance
Low-power CMOS operation
Battery monitor checks remaining capacity
daily
Industrial temperature range of -40°C to
+85°C
PACKAGE OUTLINE
Top View
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Bottom View
Side View
DESCRIPTION
The DS3816C-512 is a 524,288 x 32-advanced nonvolatile (NV) SRAM module with a 168-bump ball
grid array (BGA) pinout. The highly integrated DS3816C-512 contains a 64-byte real time clock, four
8Mb SRAMs and control circuitry which constantly monitors V
CC
for an out-of-tolerance condition.
When such a condition occurs, the DS3816C-512 makes use of an attached DS3802 Battery Cap to
maintain clock information and preserve stored data while protecting that data by disallowing all memory
accesses. Additionally, the DS3816C-512 has dedicated circuitry for monitoring the status of V
CC
and the
status of an attached DS3802 Battery Cap.
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DS3816C-512
NV SRAM READ MODE
The DS3816C-512 executes an NV SRAM read cycle whenever
WE0
–
WE3
(Write Enables) are inactive
(high), any or all of
CE0
–
CE3
(Chip Enables) are active (low) and
0E
(Output Enable) is active (low).
The unique address specified by the 19 address inputs (A
0
– A
18
) defines which of the 524,288 words of
data is accessed. The four chip enable signals (
CE0
–
CE3
) determine which bytes in the addressed word
are output on data lines DQ31 – DQ0. Valid data will be output within t
ACC
(NV SRAM Access Time)
after the last address input signal is stable, providing that
CE
and
0E
(Output Enable) access times are
also satisfied. If
CE
and
0E
access times are not satisfied, then data access must be measured from the
later occurring signal (
CE
or
0E
) and the limiting parameter is either t
CO
for
CE
or t
OE
for
0E
rather
than t
ACC
.
NV SRAM WRITE MODE
The DS3816C-512 executes an NV SRAM write cycle whenever any or all of the
WE
signals (
WE0
–
WE3
) are active (low) and any of the corresponding
CE
signals (
CE0
–
CE3
) are active (low) after all
address inputs are stable. The later occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs
must be kept valid throughout the write cycle.
WE0
–
WE3
must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initiated. The
0E
control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if output drivers are enabled (
CE
and
0E
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
CLOCK READ MODE
The DS3816C-512 executes a clock read cycle whenever
WEC
(Clock Write Enable) is inactive (high),
CEC
(Clock Chip Enable) is active (low) and
OEC
(Output Enable) is active (low). The unique clock
address specified by address inputs A
0
– A
5
defines which of the 64 bytes of data is accessed. Valid data
will be output within t
ACC
(Clock Access Time) after the last address input signal is stable, providing that
CEC
and
OEC
(Output Enable) access times are also satisfied. If
CEC
and
OEC
access times are not
satisfied, then data access must be measured from the later occurring signal (
CEC
or
OEC
) and the
limiting parameter is either t
CO
for
CEC
or t
OE
for
OEC
rather than t
ACC
. Only addresses 0 to 3 FH are
implemented in the clock address space. Accesses to clock addresses higher than 3 FH are undefined.
CLOCK WRITE MODE
The DS3816C-512 executes a clock write cycle whenever
WEC
is active (low) and
CEC
is active (low)
after all address inputs are stable. The later occurring falling edge of
CEC
or
WEC
will determine the
start of the write cycle. The write cycle is terminated by the earlier rising edge of
CEC
or
WEC
. All
address inputs must be kept valid throughout the write cycle.
WEC
must return to the high state for a
minimum recovery time (t
WR
) before another cycle can be initiated. The
OEC
control signal should be
kept inactive (high) during write cycles to avoid bus contention. However, if output drivers are enabled
(
CEC
and
OEC
active) then
WEC
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS3816C-512 provides full functional capability for V
CC
greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of V
CC
without any additional support circuitry. The
DS3816C-512 constantly monitors V
CC
. Should the supply voltage decay to V
TP
, the device
automatically write protects itself, all inputs become “don’t care,” and all outputs become high
impedance. As V
CC
falls below approximately 2.7V, a power switching circuit electrically connects an
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DS3816C-512
attached DS3802 Battery Cap to the SRAM to retain data. During power-up, when V
CC
rises above
approximately 2.7V, the power switching circuit connects external V
CC
to the SRAM and disconnects the
DS3802. Normal RAM operation can resume after V
CC
exceeds 4.5V.
BATTERY MONITORING
The DS3816C-512 automatically monitors the battery in an attached DS3802 Battery Cap on a 24-hour
time interval. Such monitoring begins within t
REC
after V
CC
rises above V
TP
and is suspended when
power failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1M
W
test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
BW
is asserted. Once asserted,
BW
remains active until the battery cap or
DS3802 is replaced. The battery is still retested after each V
CC
power-up, however, even if
BW
is active.
If the battery voltage is found to be higher than 2.6V during such testing,
BW
is a de-asserted and regular
24-hour testing resume.
BW
has an open-drain output driver.
CLOCK REGISTERS
Figure 3
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