HEF4013B
Dual D-type flip-flop
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD),
clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is
LOW and is transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.
The outputs are buffered for best system performance. The clock input’s Schmitt-trigger
action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Applications
Counters and dividers
Registers
Toggle flip-flops
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C
Type number
HEF4013BP
HEF4013BT
HEF4013BTT
Package
Name
DIP14
SO14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT402-1
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
5. Functional diagram
1SD
6
SD
D
FF1
Q
1D
5
1
1Q
1CP
3
CP
CD
Q
2
1Q
1CD
2SD
4
8
SD
D
FF2
Q
2D
9
13
2Q
2CP
11
CP
CD
Q
12
2Q
2CD
10
001aag084
Fig 1.
Functional diagram
CP
C
C
C
C
Q
C
C
D
C
C
Q
C
SD
C
CD
001aag086
Fig 2.
Logic diagram (one flip-flop)
HEF4013B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
2 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
6. Pinning information
6.1 Pinning
1Q
1Q
1CP
1CD
1D
1SD
V
SS
1
2
3
4
5
6
7
001aag085
14 V
DD
13 2Q
12 2Q
HEF4013B
11 2CP
10 2CD
9
8
2D
2SD
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Symbol
1Q, 2Q
1Q, 2Q
1CP, 2CP
1CD, 2CD
1D, 2D
1SD, 2SD
V
SS
V
DD
Pin description
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
Description
true output
complement output
clock input (LOW to HIGH edge-triggered)
asynchronous clear-direct input (active HIGH)
data input
asynchronous set-direct input (active HIGH)
ground (0 V)
supply voltage
7. Functional description
Table 3.
Control
nSD
H
L
H
L
L
[1]
Function table
[1]
Input
nCD
L
H
H
L
L
nCP
X
X
X
nD
X
X
X
L
H
Output
nQ
H
L
H
L
H
nQ
L
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition.
HEF4013B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
3 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP14
SO14
TSSOP14
P
[1]
[2]
[3]
[1]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
-
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+125
750
500
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
mW
power dissipation
per output
For DIP14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above T
amb
= 60
C,
P
tot
derates linearly with 5.5 mW/K.
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4013B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
4 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
10. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level
input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level
output voltage
I
O
< 1
A
5V
10 V
15 V
V
OL
LOW-level
output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level
output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level
output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage
current
supply current
all valid input
combinations;
I
O
= 0 A
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
10 V
15 V
-
T
amb
=
40 C
T
amb
= +25
C
T
amb
= +85
C
T
amb
= +125
C
Unit
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.64
1.6
4.2
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
-
0.1
1.0
2.0
4.0
-
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.5
1.3
3.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
-
0.1
1.0
2.0
4.0
7.5
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
30
60
120
-
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
30
60
120
-
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
C
I
input
capacitance
HEF4013B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
5 of 16
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