ST72F521AR6TCRS datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ST72F521AR6TCRS

ST72F521AR6TCRS: Description8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，276 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST72F521AR6TCRS Overview

8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

ST72F521AR6TCRS Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	10 X 10 MM, ROHS COMPLIANT, LQFP-64
Contacts	64
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	ST72
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G64
length	10 mm
Number of I/O lines	48
Number of terminals	64
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	1024
rom(word)	32768
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	8 MHz
Maximum slew rate	15 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	3.8 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72521xx-Auto

8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,

ADC, 5 timers, SPI, SCI, I2C, CAN interface

Features

Memories

■

32 to 60 Kbyte dual voltage High Density Flash

(HDFlash) or ROM with readout protection

capability. In-application programming and in-

circuit programming for HDFlash devices

■

1 to 2 Kbyte RAM

■

HDFlash endurance: 100 cycles, data retention

20 years

LQFP80

14 x 14

LQFP64

14 x 14

LQFP64

10 x 10

5 timers

■

Clock, reset and supply management

■

Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

■

Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and bypass

for external clock

■

PLL for 2x frequency multiplication

■

4 power saving modes: Halt, Active Halt, Wait

and Slow

Main clock controller with Real-time base,

Beep and Clock-out capabilities

■

Configurable watchdog timer

■

Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1

timer, PWM and pulse generator modes

■

8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare and

time base interrupt, external clock with event

detector

4 communications interfaces

■

Interrupt management

■

Nested interrupt controller

■

14 interrupt vectors plus TRAP and RESET

■

Top Level Interrupt (TLI) pin

■

15 external interrupt lines (on 4 vectors)

SPI synchronous serial interface

■

SCI asynchronous serial interface

■

I C multimaster interface (SMbus V1.1

compliant)

■

CAN interface (2.0B passive)

Instruction set

■

Analog peripheral

■

10-bit ADC with up to 16 input ports

Up to 64 I/O ports

■

8-bit data manipulation

■

63 basic instructions

■

17 main addressing modes

■

8x8 unsigned multiply instruction

48 multifunctional bidirectional I/O lines

■

34 alternate function lines

■

16 high sink outputs

Development tools

■

Full HW/SW development pkg, ICT capability

Device summary

Part number

Table 1.

Reference

ST72521R6-Auto

ST72521R9-Auto

ST72521xx-Auto

ST72521AR9-Auto

ST72521M9-Auto

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Contents

ST72521xx-Auto

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1

2.2

Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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Contents

6.4

6.5

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 44

Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 50

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.1

7.2

7.3

7.4

7.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.5.1

7.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 57

7.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.6.1

7.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 62

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.1

8.2

8.3

8.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.4.1

8.4.2

Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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Contents

ST72521xx-Auto

9.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.3

9.4

9.5

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 83

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.9.1

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Main clock controller with real-time clock and beeper (MCC/RTC) . . 85

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.8.1

11.8.2

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87

MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 88

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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ST72521xx-Auto

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

12.2.9

Contents

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 93

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 93

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.3

ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . . 99

Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.1

13.2

13.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.3.1

13.3.2

13.3.3

13.3.4

13.3.5

13.3.6

13.3.7

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.4

13.5

13.6

13.7

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

13.7.1

13.7.2

13.7.3

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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My 2015 ——— Write a year-end summary to win a New Year’s surprise!: [i=s]This post was last edited by jiming on 2016-1-12 19:02[/i] [align=left] [align=left][font=微软雅黑][size=4] [/size][/font][font=微软雅黑][size=5] [/size][/font]{:1_106:}[font=微软雅黑][size=5]It has been ten...; jiming Talking

Wavelet Analysis and Its Application in Image Processing: ...; mayulan DSP and ARM Processors

A matching problem?: I used an op amp to build a two-stage amplifier circuit, with direct coupling, and there was a signal attenuation problem. Because I used pspice simulation, I didn't need to consider the influence of ...; cwzplay Analog electronics

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