data sheet
January 1998
Revision 1.0
PDC16UV6484A-(103/10)T-S
128MByte (16M x 64) CMOS, PC/100
Synchronous DRAM Module
General Description
The PDC16UV6484A-(103/10)T-S is a high performance, 64-megabyte synchronous, dynamic RAM module organized as 16M
words by 64 bits, in a 168-pin, dual-in-line memory module (DIMM) package.
The module utilizes sixteen Fujitsu MB81F64842B-(103/10)FN CMOS 8Mx8 synchronous dynamic RAMs in surface mount
package (TSOP) on an epoxy laminated substrate. Each device is accompanied by a decoupling capacitor for improved noise
immunity.
A 256 Byte Serial EEPROM contains the module configuration information.
Features
• High Density
• Cycle Time:
• Low Power:
128MByte
10ns (-103), 10ns (-10)
Active 7.2W (-103), 6.0W (-10)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.375 inch
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperate
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
-0.5 to +4.6
16.0
0 to +70
-55 to +125
Unit
V
W
°
C
°
C
mA
±
50
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70
°C)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High voltage
Input Low voltage
Min
3.0
0
2.0
-0.5
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.5
0.8
Unit
V
V
V
V
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
1
January 1998
Revision 1.0
PDC16UV6484A-(103/10)T-S
Functional Diagram
DQMB7
DQMB6
DQMB3
DQMB2
DQMB5
DQMB4
DQMB1
DQMB0
CKE0
CS0*
CLK0
BA0
BA1
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
CS2*
CLK2
CKE1
CS1*
CLK1
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
8Mx8
SDRAM
CS3*
CLK3
DQ0~DQ7
DQ8~DQ15
DQ32~DQ39
DQ40~DQ47
DQ16~DQ23
DQ24~DQ31
DQ48~DQ55
DQ56~DQ63
DQ0~DQ63
0.1µF
SA0-SA2
SCL
A0-A2
SCL
SDA
SDA
WP
47KΩ
V
CC
V
SS
EEPROM
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1.
2.
3.
4.
A0~A11 to all devices
WE*, RAS*, CAS* to all devices.
Data and CLKs are terminated using 10 ohm series resistors.
CKE1 has a 10KΩ pull-up to Vcc
Vcc
10KΩ
CKE1
CKE
5.
DQMs vs. Data I/Os
DQMB0 controls DQ0~DQ7
DQMB1 controls DQ8~DQ15
DQMB2 controls DQ16~DQ23
DQMB3 controls DQ24~DQ31
DQMB4 controls DQ32~DQ39
DQMB5 controls DQ40~DQ47
DQMB6 controls DQ48~DQ55
DQMB7 controls DQ56~DQ63
6.
Clock Wiring
SDRAM1
SDRAM2
SDRAM3
SDRAM4
3.3pF
10Ω
CLK0, CLK1, CLK2, CLK3
2
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
January 1998
Revision 1.0
PDC16UV6484A-(103/10)T-S
Pin Name
A0~A11
BA0, BA1
DQ0~DQ63
CLK0~CLK3
RAS*
CAS*
CKE0, CKE1
DQMB0-DQMB7
Addresses
Bank Select Address
Data Inputs/Outputs
Clock Inputs
Row Address Strobes
Column Address Strobes
Clock Enables
DQ Mask Enables
CS0*~CS3*
WE*
SA0~SA2
SCL
SDA
WP
V
CC
V
SS
NC
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin Designation
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
CC
CAS*
DQMB4
DQMB5
CS1*
RAS*
V
SS
A1
A3
A5
A7
A9
BA0 (Note)
A11
V
CC
CLK1
NC
Chip Select
Write Enable
Decode Input
Serial Clock
Serial Data Input/Output
Write Protect
Power Supply
Ground
No Connection
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin Designation
V
SS
CKE0
CS3*
DQMB6
DQMB7
NC
V
CC
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
V
CC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Designation
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
NC
NC
V
SS
NC
NC
V
CC
WE*
DQMB0
DQMB1
CS0*
NC
V
SS
A0
A2
A4
A6
A8
A10 / AP (Note)
BA1 (Note)
V
CC
V
CC
CLK0
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Designation
V
SS
NC
CS2*
DQMB2
DQMB3
NC
V
CC
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
SDA
SCL
V
CC
Note : 1. Address A10 / AP : Initiates Auto Precharge
2. Address BA0,BA1 : Bank select within the SDRAM devices
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
3
January 1998
Revision 1.0
PDC16UV6484A-(103/10)T-S
SERIAL PD INFORMATION
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Function Described
# Bytes Written into serial memory at module mfr
Total # bytes of SPD memory device
Fundamental memory type
# Row Address on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly
Data Width of this assembly (continued)
Voltage interface standard of this assembly
SDRAM cycle time at CL=3 (tCLK)
SDRAM Access from Clock at CL=3 (tAC)
DIMM configuration type
Refresh Rate/Type
SDRAM Width Primary DRAM
ECC SDRAM Data Width
Min. clock delay, Back to Back Random Column
Addresses (ICCD)
Burst Length Supported
# Banks on each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attribute
SDRAM Device Attribute
Min Clock cycle Time at CL=2 (tCLK)
Max. Data Access Time from clock at CL=2 (tAC)
Min Clock cycle Time at CL=1 (tCLK)
Max. Data Access Time from clock at CL=1 (tAC)
Min. Row Precharge Time (tRP)
Min. Row Active Delay (tRRD)
Min. RAS to CAS Delay (tRCD)
Min. RAS Pulse Width (tRAS)
Module Bank Density
Add. & CMD Input Setup Time (tSI)
Add. & CMD Input Hold Time (tHI)
Data Input Setup Time (tSI)
Data Input Hold Time (tHI)
Superset Information
SPD Revision
Checksum for bytes 0-62
Function Supported
-103
-10
128 bytes
256 bytes
SDRAM
12
9
2
64 bits
LVTTL
10ns
6ns
Non-Parity
S/R, Normal 15.6 ms
x8
N/A
1CLK
1, 2, 4, 8 & Full
4
2, 3
0
0
Non-Buffered/Registered
Vcc, B/R, S/W, P/A, A/P
15ns
8.0ns
N/A
N/A
20ns
30ns
20ns
20ns
30ns
50ns
64MB
2ns
1ns
2ns
1ns
Rev. 2
JEDEC Calculation
Hex Value
-103
80h
08h
04h
0Ch
09h
02h
40h
00h
01h
A0h
60h
00h
80h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
F0h
80h
FFh
FFh
14h
14h
14h
1Eh
32h
10h
20h
10h
20h
10h
FFh
02h
JEDEC Calculation
1Eh
-10
4
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
January 1998
Revision 1.0
PDC16UV6484A-(103/10)T-S
SERIAL PD INFORMATION (CONTINUED)
Function Supported
Byte#
64
65
66-71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95-98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128-255
Hex Value
-103
7Fh
94h
FFh
50h
44h
43h
31h
36h
55h
56h
36h
34h
38h
34h
41h
31h
30h
33h
54h
53h
31h
30h
54h
53h
FFh
Function Described
Manufacturers JEDEC ID code per JEP-106E
Manufacturers JEDEC ID code per JEP-106E
Manufacturers JEDEC ID code per JEP-106E
Manufacturing location
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Manufacturer’s Part Number
Revision Code
Revision Code
Manufacturing Date
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Manufacturer Specific Data
Open for CPQ Use for Read & Write
-103
-10
-10
Continuation code
SMART’s ID
None
Mfr Specific Data
P
D
C
1
6
U
V
6
4
8
4
A
1
0
3
T
S
1
0
T
S
None
None
Mfr Specific Data
None
DATE
DATE
Serial Number
S
M
A
R
T
M
o
d
u
l
a
r
T
e
c
h
n
o
l
o
g
i
e
s
None
None
None
None
None
None
FFh
Mfr Specific Data
FFh
DATE
DATE
S.No.
53h
4Dh
41h
52h
54h
4Dh
6Fh
64h
75h
6Ch
61h
72h
54h
65h
63h
68h
6Eh
6Fh
6Ch
6Fh
67h
69h
65h
73h
FFh
FFh
FFh
FFh
FFh
FFh
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
5