Standard Products
ACT-D16M96S High Speed 16MegaBit x 96 3.3V
Synchronous DRAM Multichip Module
www.aeroflex.com/Avionics
September 9, 2009
FEATURES
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Six (6) low power 4M x 16 x 4 banks Synchronous Dynamic Random Access Memory chips in one MCM
Configured as "2" independent 4M x 48 x 4 bank
High-Speed, low-noise, low-voltage TTL (LVTTL) interface
3.3-V Power supply (±5% tolerance)
Separate logic and output driver power pins
Up to 50-MHz data rates
Internal pipelined operation; column address can be changed every clock cycle
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge, and auto refresh modes
Self refresh mode
64ms, 8,192-cycle refresh
CAS latency (CL) programmable to 2 cycles from column-address entry
Cycle-by-Cycle DQ-bus write mask capability with upper and lower byte control
Chip select and clock enable for enhanced-system interfacing
Designed for commercial, industrial and aerospace applications
MIL-PRF-38534 compliant devices available
Aeroflex-Plainview is a Class H & K MIL-PRF-38534 manufacturer
200-Lead, hermetic, CQFP, cavity-up package
GENERAL DESCRIPTION
The ACT-D16M96S device is a high-speed synchronous dynamic random access memory (SDRAM) organized as
2 independent 4M x 48 x 4 banks. All inputs and outputs of the ACT-D16M96S are compatible with the LVTTL interface.
All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
SCD3370 Rev D
S
E
C
T
I
O
N
A
CS1
CLK1
CKE1
DQMU1
DQML1
RAS1
CAS1
WE1
A0-A12
BSA0
BSA1
B
ANKA0-3
13
4M x 16 x 4 Banks
16
4M x 16 x 4 Banks
16
4M x 16 x 4 Banks
16
DQ
0-15
CS2
CLK2
CKE2
DQMU2
DQML2
RAS2
CAS2
WE2
BA0-BA12
BSB0
BSB1
B
ANKB0-3
DQ
16-31
DQ
32-47
S
E
C
T
I
O
N
B
13
4M x 16 x 4 Banks
16
4M x 16 x 4 Banks
16
4M x 16 x 4 Banks
16
DQ
48-63
DQ
64-79
DQ
80-95
FIGURE 1 – Block Diagram
SCD3370 Rev D 9/9/09
Aeroflex Plainview
2
Functional Description
There are six (6) 256Mb SDRAMs (4 Meg x 16 x 4 banks) chips that operate at 3.3V and include a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 8,192
rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BSA0, BSA1, BSB0, BSB1 select the bank, A0-A12; BA0–BA12 select the row). The
address bits (x16: A0-A8; BA0–BA8) registered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering
device initialization, register definition, command descriptions, and device operation.
For additional Detail Information regarding the operation of the individual chip (MT48LC16M16A2 – 4 Meg x 16 x 4 banks)
see Micron 524,288-WORD BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
Datasheet Revision M dated 1/09 or contact the Aeroflex Sales Department.
SCD3370 Rev D 9/9/09
Aeroflex Plainview
3
Absolute Maximum Ratings
1
Symbol
V
CC
V
CCQ
V
RANGE
T
BIAS
T
STG
P
W
Rating
Supply Voltage
Supply Voltage range for output drivers
Voltage range on any pin with respect to V
SS
Junction Temperature under Bias
2
Storage Temperature
Power Dissipation
Range
-0.5 to 4.6
-0.5 to 4.6
-0.5 to 4.6
-55 to +125
-65 to +150
4.2
Units
V
V
V
°C
°C
W
1. Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Tested with Case set to specified temperature. The temperature rise of
θ
jc
is negligible due to the low duty cycle during testing.
Recommended Operating Conditions
Symbol
V
CC
V
CCQ
V
SS
V
SSQ
V
IH
V
IL
T
C
Parameter
Supply Voltage
Supply Voltage range for output drivers
Supply Voltage
Supply Voltage range for output drivers
Input High Voltage
Input Low Voltage
1
Operating Temperature (Junction)
2
Min
3.15
3.15
-
-
2
-0.3
-55
Ty
3.3
3.3
0
0
-
-
-
Max
3.45
3.45
-
-
V
CC
+ 0.3
0.8
+107
Units
V
V
V
V
V
V
°C
Notes:
1. V
IL
Minimum = 1.5Vac (Pulsewidth < 5ns)
2. Tested with Case set to specified temperature. The temperature rise of
θ
jc
is negligible due to the low duty cycle during testing and it is
recommended that the maximum junction temperature should be kept less then +110°C.
Thermal Impedance
Parameter
Junction to Case
θ
jc
1.53
Units
°C/W
Model based on Micron die database Y16Y and die size - 5,250.010µm x 8,879.002µm (206.693 mil x 349.567 mil) using Aeroflex
ceramic co-cired package 25G5060 Rev B.
DC Characteristics
(V
CC
= 3.3V ±0.15; T
J
=-55°C to +107°C, See Notes 1 & 5)
Parameter
Output Low Voltage
Output High Voltage
Input current (Leakage)
Output current (Leakage)
Precharge standby current
in non-power-down mode
Symbol
V
OL
V
OH
I
I
I
O
I
CC
2
N
I
CC
2
NS
Conditions
I
OL
= 2mA
I
OH
= -2mA
0V < V
I
< V
CC
+ 0.3V, All other pins = 0V to V
CC
0V < V
O
< V
CC
+ 0.3V, Output disabled
CKE > V
IH
MIN,
t
CK
= 20ns (See Note 2)
CKE > V
IH
MIN, CLK < V
IL
MAX,
t
CK
=
∞,
(See Note 3)
Min
-
2.4
-10
-10
-
-
Max
0.4
-
+10
+10
180
120
Units
V
V
µA
µA
mA
mA
Notes:
1. All specifications apply to the device after power- up initialization. All control and address inputs must be stable and valid.
2. Control, DQ, and address inputs change state only once every 40 ns.
3. Control, DQ, and address inputs do not change (stable).
4. All I
CC
parameters measured with V
CC
, not V
CCQ
.
5. Tested with Case set to specified temperature. The temperature rise of
θ
jc
is negligible due to the low duty cycle during testing.
SCD3370 Rev D 9/9/09
Aeroflex Plainview
4
Capacitance†
(f = 1MHz, Tc = 25°C)
Symbol
C
i(S)
C
i(AC)
C
i(E)
C
O
†
Parameter
Input Capacitance, CLK Input
Input Capacitance, Address and Control Inputs: A0-A11, CS, DQMx, RAS, CAS, WE
Input Capacitance, CKE Input
Output Capacitance
Min
-
-
-
-
Max
50
40
50
20
Units
pF
pF
pF
pF
Parameters Guaranteed but not tested.
AC Timing†‡
(Vcc = 3.3V ±0.15V, T
J
= -55°C to +107°C, See Note 4)
Parameter
Cycle time, CLK
Pulse duration, CLK high
Pulse duration, CLK low
Access time, CLK high to data out (see Note 1)
Hold time, CLK high to data out
Setup time, address input
Setup time, banksel input
Setup time, data input
Setup time, control input
Hold time, address, control, and data input
Delay time, ACTV command to DEAC or DCAB
command
Delay time, ACTV or REFR to ACTV, MRS or
REFR command
Delay time ACTV command to READ, READ-P,
WRT, or WRT-P command (see Note 2)
Delay time, DEAC or DCAB command to ACTV,
MRS or REFR command
Delay time, ACTV command in one bank to ACTV
command in the other bank
Delay time, MRS command to ACTV, MRS or
REFR command
Final data out of READ-P operation to ACTV,
MRS or REFR command
Symbol
Test Conditions
CAS latency = 2
Min
20
5
5
CAS latency = 2
-
1
3
3
2.5
2.5
2.5
72
100
2 * 12.5ns Cycles
2 * 12.5ns Cycles
25
25
18
30
Max
-
-
-
13
-
-
-
-
-
-
100000
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK2
t
CH
t
CL
t
AC2
t
OH
t
IS[addr]
t
IS[banksel]
t
IS[data]
t
IS[cntrl]
t
IH
t
RAS
t
RC
t
RCD
t
RP
t
RRD
t
RSA
t
APR
Min
-
t
RP - (CL -1) *
t
CK
(See Note 3)
SCD3370 Rev D 9/9/09
Aeroflex Plainview
5
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