Revision 8
ACT 2 Family FPGAs
Features
• Up to 8,000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL
®
Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequence Functions
• Wide-Input Combinatorial Functions
• Up to 1,232 Programmable Logic Modules
• Up to 998 Flip-Flops
Table 1 • ACT 2 Product Family Profile
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
Logic Modules
S-Module
C-Module
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
User I/Os (maximum)
Performance
1
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
Packages
2
CPGA
PLCC
PQFP
VQFP
TQFP
CQFP
PG100
PL84
PQ100
VQ100
–
–
PG132
PL84
PQ144
–
TQ176
–
PG176
PL84
PQ160
–
TQ176
CQ172
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
85 MHz
67 MHz
36 MHz
36
15
250,000
83
36
15
400,000
104
36
15
750,000
140
2,500
6,250
63
25
451
231
220
382
4,000
10,000
100
40
684
348
336
568
8,000
20,000
200
80
1,232
624
608
998
A1225A
A1240A
A1280A
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0 micron CMOS Technology
Notes:
1. Performance is based on –2 speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1,
Version 1.2, dated 3-28-93. Any analysis is not endorsed by PREP.
2. See the
"Product Plan" on page III
for package availability.
January 2012
© 2012 Microsemi Corporation
I
ACT 2 Family FPGAs
Ordering Information
A1280
A
_
1
PG
G
176
C
Application (T emperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0
μm
CMOS Process
Part Number
A1225 = 2,500 Gates
A1240 = 4,000 Gates
A1280 = 8,000 Gates
II
R ev i si o n 8
ACT 2 Family FPGAs
Product Plan
Speed Grade
1
Device/Package
A1225A Device
84-Pin Plastic Leaded Chip Carrier (PL)
100-Pin Plastic Quad Flatpack (PQ)
100-Pin Very Thin Quad Flatpack (VQ)
100-Pin Ceramic Pin Grid Array (PG)
A1240A Device
84-Pin Plastic Leaded Chip Carrier (PL)
132-Pin Ceramic Pin Grid Array (PG)
144-Pin Plastic Quad Flat Pack (PQ)
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
A1280A Device
160-Pin Plastic Quad Flatpack (PQ)
172-Pin Ceramic Quad Flatpack (CQ)
176-Pin Ceramic Pin Grid Array (PG)
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
Notes:
1. Applications:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
Std.
–1
–2
C
Application
1
I
M
B
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
–
–
–
–
–
–
–
–
–
✓
–
–
–
✓
–
–
✓
–
–
✓
–
✓
–
–
–
–
–
✓
✓
–
✓
✓
–
Availability:
✓
= Available
P = Planned
– = Not planned
Speed Grade:
–1 = Approx. 15% faster than Std.
–2 = Approx. 25% faster than Std.
2. Contact your Microsemi SoC Products Group sales representative for product availability.
Device Resources
Device
Series
A1225A
A1240A
A1280A
Logic
Modules
451
684
1,232
User I/Os
Gates
2,500
4,000
8,000
PG176
–
–
140
PG132
–
104
–
PG100
83
–
–
PQ160
–
–
125
PQ144
–
104
–
PQ100
83
–
–
PL84
72
72
72
CQ172
–
–
140
TQ176
–
104
140
VQ100
83
–
–
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
R e visi on 8
III
ACT 2 Family FPGAs
Table of Contents
ACT 2 Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Detailed Specifications
Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
ACT 2 Timing Model
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Package Pin Assignments
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
PG176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Revision 8
IV
1 – ACT 2 Family Overview
General Description
The ACT 2 family represents Actel’s second generation of
field programmable gate arrays
(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-
modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family provides significant enhancements to gate
density and performance while maintaining downward compatibility with the ACT 1 design environment
and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon
gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary
architecture offers gate array design flexibility, high performance, and fast time-to-production with user
programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which
offers automatic pin assignment, validation of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are
supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems
provide CAE interfaces to the following design environments: Cadence, Viewlogic
®
,
Mentor Graphics
®
,
and OrCAD™.
Revision 8
1 -1
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
