P
RELIMINARY
P
R O D U C T
B
R I E F
IEC4-T
PEF 24901 V2.1 (DFE-T)
PEF 24902 V2.1 (AFE)
ISDN Echocancellation Circuit
4-Channel for 4B3T Line Code
The widely used ISDN 4-channel chipset IEC4-T
consisting of the analog frontend PEB/F 24902
(AFE) and the digital frontend PEB/F 24901
(DFE-T) has been optimized by a redesign of the
digital part. The improvements of the DFE-T are a
reduced supply-voltage due to its advanced low
power 3.3V-CMOS-technology, the doubling of the
IOM
®
-2 data-rate up to 4 Mbit/s and new features in
terms of testability and analysis. The IEC4-T
chipset fulfills all relevant FTZ, ETSI and ITU stan-
dards. Because of its multichannel-architecture it
is extremely suitable for highly integrated
ISDN linecards.
Applications
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Central office digital linecard
Access network linecards
PBX linecards
s
Features
s
s
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Two chip solution featuring full
duplex data transmission and
reception over two-wire metallic
subscriber loops providing 4x
ISDN basic rate access
Fully compliant to:
- FTZ Guideline 1TR220
- ETSI TS 102 080 (1998)
- Recommendation ITU-T I.430
4B3T block code at 120 kHz
symbol rate
Loop length without repeater:
- up to 4.2 km on 0.4 mm wire
- up to 8.0 km on 0.6 mm wire
LT mode
s
s
s
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Low power consumption
IOM
®
-2 interface for
stand alone mode
1 kbit/s maintenance channel for
transmission of data loopback
commands and detected
transmission errors
Masterclock generated by PLL
Activation and deactivation
Adaptive echo cancellation and
equalization
Automatic gain control and
polarity adaption
4 relay driver pins per channel to
switch relays or power controller
2 status pins per channel
Extended temperature range
(40°C to +85°C)
JTAG Boundary Scan
P-MQFP-64 package
Part of the Infineon
System Solution
Add-On Features of the DFE-T
PEF 24901 V2.1 compared to V1.x
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Max. IOM
®
-2 data rate 4 Mbit/s
(DCL = 8 MHz)
+3.3 V instead of +5 V
power supply
Dedicated pins for SSP and
DT test modes
DOUT configurable either as
open drain or push-pull
(tristate) output
New MON-12 class features
internal register access
Additional digital local loops
Bit Error Rate Measurement
per port
Optimized LT-state machine
Backward compatibility to V1.x:
- no software changes required
- pinning-compatible
ISDN
I S D N
4-Channel Chipset
N e v e r
s t o p
t h i n k i n g .
P
Block Diagram
AFE V2.1
LIU
DAC
Hybrid
R O D U C T
B
R I E F
DFE-T V2.1
DSP
U Protocol Processing Unit
4B3T
Encoder
Echo
Canceller
Σ∆
ADC
PDM
Filter
-
+
AGC
Equalizer
4B3T
Decoder
De-
Scrambler
U De-
Framing
Scrambler
U Framing
System
Interface
Unit
IOM
®
-2
SIU
4xU
Level Detection
for Wake Up
Bandgap,
Bias, Refer.
Timing
Recovery
Activation/Deactivation Controller
Clock Generation
Mode Setting
I/O Control
Clocks
Mode Pins
General Purpose I/Os
Type
PEF 24901 H V2.1
PEB/F 24902 H V2.1
Package
P-MQFP-64
P-MQFP-64
Availability
Development
Available
Tools and Documentation
Name
Preliminary Data Sheet PEF 24901 V2.1
Delta Sheet PEF 24901 V2.1
Product Overview
Smart 24901 V2.0
Status
06.99
03.99
04.99
Development
Test Unit
1
2
3
4
Q-IHPC
PEB 2426
RAM
µC
AFE
V2.1
PEF 24902
DFE-T
V2.1
PEF 24901
IOM
®
-2
PCM HW
DELIC-PB
PEB 20571
Signaling
Application Examples
ISDN Linecard
V
BAT
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descriptions and charts stated herein.
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Printed in Germany
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NB
Published by Infineon Technologies AG