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GS8662Q09E-200T

Description
Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
Categorystorage    storage   
File Size1MB,34 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS8662Q09E-200T Overview

Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

GS8662Q09E-200T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeBGA
package instruction15 X 17 MM, 1 MM PITCH, FPBGA-165
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time0.45 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PBGA-B165
length17 mm
memory density75497472 bit
Memory IC TypeSTANDARD SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8MX9
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width15 mm
GS8662Q08/09/18/36E-278/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaQuad-II
Burst of 2 SRAM
Clocking and Addressing Schemes
278 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
SigmaQuad™ Family Overview
The GSQ8662Q08/09/18/36E are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
me
nd
ed
for
-278
Ne
w
Parameter Synopsis
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
tKHKH
3.6 ns
tKHQV
0.45 ns
Rev: 1.09a 11/2011
No
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Re
co
m
.
1/34
De
sig
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Di
sco
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inu
ed
Pr
od
u
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 8M x 8 has an 4M addressable
index).
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2005, GSI Technology
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