FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ICS843003I-09
General Description
The ICS843003I-09 is a 3 differential output
ICS
LVPECL Synthesizer designed to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from IDT. Using a 25MHz, 18pF parallel
resonant crystal, the following frequencies can be generated:
156.25MHz and 125MHz. The 843003I-09 has two output banks,
Bank A with one differential LVPECL output pair and Bank B with
two differential LVPECL output pairs.
The ICS843003I-09 uses IDT’s 3 generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements. The
ICS843003I-09 is packaged in a small 24-pin TSSOP, EPad
package.
rd
Features
•
•
•
•
•
•
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Three 3.3Vdifferential LVPECL output pairs on two banks:
Bank A with one LVPECL output pair
Bank B with two LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended reference clock input
VCO range: 490MHz – 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz):
0.53ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
OEA
Pullup
VCO_SEL
Pullup
REF_CLK
Pulldown
25MHz
Pin Assignment
QA0
0
nQA0
0
÷4
nc
VCO_SEL
MR
V
CCO_A
QA0
nQA0
OEB
OEA
nc
V
CCA
V
CC
nc
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nc
V
CCO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
V
EE
nc
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
QB0
nQB0
÷25
÷5
QB1
nQB1
ICS843003I-09
24-Lead TSSOP, EPad
4.4mm x 7.8mm x 0.9mm
package body
G Package
Top View
MR
Pulldown
OEB
Pullup
IDT™ / ICS™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843003BGI-09 REV. A APRIL 17, 2008
ICS843003I-09
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 9, 12, 13, 24
Name
nc
Unused
Type
Description
No connect.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed by
default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs QX to go low and the inverted outputs nQX to go
high. When logic LOW, the internal dividers and the outputs are enabled. MR
has an internal pulldown resistor so the power-up default state of the outputs
and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Bank B output enable pin. Active High output enable. When logic HIGH, the 2
output pairs on Bank B are enabled. When logic LOW, the output pairs drive
differential Low (QBx = Low, nQBx = High). OEB has an internal pullup
resistor so the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Bank A output enable pin. Active High output enable. When logic HIGH, the
output pair on Bank A is enabled. When logic LOW, the output pair drives
differential Low (QA0 = Low, nQA0 = High). OEA has an internal pullup
resistor so the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Negative supply pin.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Pulldown
Pullup
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5, 6
V
CCO_A
QA0, nQA0
Power
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
10
11
14
15,
16
17
18
19, 20
21, 22
23
V
CCA
V
CC
V
EE
XTAL_OUT,
XTAL_IN
REF_CLK
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
CCO_B
Power
Power
Power
Input
Input
Input
Output
Output
Power
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
IDT™ / ICS™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843003BGI-09 REV. A APRIL 17, 2008
ICS843003I-09
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Bank A Frequency Table
Input
Crystal Frequency (MHz)
25
24
20
Feedback Divider
25
25
25
Bank A Output
Divider
4
4
4
QA0/nQA0
Output Frequency (MHz)
156.25
150
125
M/N Multiplication Factor
6.25
6.25
6.25
Table 3B. Bank B Frequency Table
Input
Crystal Frequency (MHz)
25
Feedback Divider
25
Bank B Output
Divider
5
QB[0:1]/nQB[0:1]
Output Frequency (MHz)
125
M/N Multiplication Factor
5
Table 3C. OEA Select Function Table
Input
OEA
0
1
QA0
LOW
Active
Outputs
nQA0
HIGH
Active
Table 3D. OEB Select Function Table
Input
OEB
0
1
Outputs
QB0, QB1
LOW
Active
nQB0, nQB1
HIGH
Active
Disabled
REF_CLK
Enabled
OEA, OEB
nQA0, nQB0, nQB1
QA0, QB0, QB1
Figure 1. OE Timing Diagram
IDT™ / ICS™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843003BGI-09 REV. A APRIL 17, 2008
ICS843003I-09
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
32.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
20
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
MR, REF_CLK
Input High Current
OEA, OEB,
VCO_SEL, XTAL_SEL
MR, REF_CLK
I
IL
Input Low Current
OEA, OEB,
VCO_SEL, XTAL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
IDT™ / ICS™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843003BGI-09 REV. A APRIL 17, 2008
ICS843003I-09
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 4C. LVPECL DC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_A/B
– 1.4
V
CCO_A/B
– 2.0
0.6
Typical
Maximum
V
CCO_A/B
– 0.9
V
CCO_A/B
– 1.7
1.0
Units
µA
µA
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_A, _B
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
19.6
Test Conditions
Minimum
Typical
Fundamental
27.2
50
7
1
MHz
Maximum
Units
Ω
pF
mW
AC Electrical Characteristics
Table 6. AC Characteristics,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Parameter
f
OUT
Symbol
Output Frequency Range
Test Conditions
÷4
÷5
156.25MHz,
(1.875MHz – 20MHz)
125MHz,
(1.875MHz – 20MHz)
20% to 80%
200
45
Minimum
122.5
98
0.53
0.48
50
600
55
Typical
Maximum
170
136
Units
MHz
MHz
ps
ps
ps
ps
%
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
Bank Skew; NOTE 2
Output Rise/Fall Time
Output Duty Cycle
tsk(b)
t
R
/ t
F
odc
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
IDT™ / ICS™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843003BGI-09 REV. A APRIL 17, 2008
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