TU24C64CP3 datasheet, PDF - EEWORLD Datasheet

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TU24C64CP3: DescriptionCMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM; File Size49KB，8 Pages; ManufacturerETC

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TU24C64CP3 Overview

CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM

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Turbo IC, Inc.

24C64

CMOS I²C 2-WIRE BUS

64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM

8K X 8 BIT EEPROM

FEATURES :

• Extended Power Supply Voltage

Single Vcc for Read and Programming

(Vcc = 2.7 V to 5.5 V)

• Low Power (Isb = 2µa @ 5.5 V)

• Extended I²C Bus, 2-Wire Serial Interface

• Support Byte Write and Page Write (32 Bytes)

• Automatic Page write Operation (maximum 10 ms)

Internal Control Timer

Internal Data Latches for 32 Bytes

• Hardware Data Protection by Write Protect Pin

• High Reliability CMOS Technology with EEPROM Cell

Endurance : 1,000,000 Cycles

Data Retention : 100 Y

ears

DESCRIPTION:

The Turbo IC 24C64 is a serial 64K EEPROM fabricated

with Turbo’s proprietary, high reliability, high performance

CMOS technology. It’s 64K of memory is organized as 8,192

x 8 bits. The memory is configured as 256 pages with each

page containing 32 bytes. This device offers significant ad-

vantages in low power and low voltage applications.

The Turbo IC 24C64 uses the extended I²C addressing pro-

tocol and 2-wire serial interface which includes a bidirec-

tional serial data bus synchronized by a clock. It offers a

flexible byte write and a faster 32-byte page write. The data

in the upper quadrant of memory can be protected by a

write protect pin.

The Turbo IC 24C64 is assembled in either a 8-pin PDIP or

8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are

device address input pins which are hardwired by the user.

Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA)

pin used for bidirectional transfer of data. Pin #6 is the serial

clock (SCL) input pin. Pin #7 is the write protect (WP) input

pin, and Pin #8 is the power supply (Vcc) pin.

PIN DESCRIPTION

All data is serially transmitted in bytes (8 bits) on the SDA

bus. To access the Turbo IC 24C64 (slave) for a read or

write operation, the controller (master) issues a start condi-

tion by pulling SDA from high to low while SCL is high. The

master then issues the device address byte which consists

of 1010 (A2) (A1) (A0) (R/W). The 4 most significant bits

(1010) are a device type code signifying an EEPROM de-

vice. The A[2:0] bits represent the input levels on the 3 de-

vice address input pins. The read/write bit determines

whether to do a read or write operation. After each byte is

transmitted, the receiver has to provide an acknowledge by

pulling the SDA bus low on the ninth clock cycle. The ac-

knowledge is a handshake signal to the transmitter indicat-

ing a successful data transmission.

drain output. A pullup resistor must be connected

from SDA to Vcc.

SERIAL

CLOCK (SCL)

The SCL input synchronizes the data on the SDA

bus. It is used in conjunction with SDA to define

the start and stop conditions. It is also used in

conjunction with SDA to transfer data to and from

the Turbo IC 24C64.

GND

VCC

SCL

SDA

GND

VCC

SCL

SDA

8 pin SOIC

8 pin PDIP

PIN DESCRIPTION

DEVICE ADDRESSES (A2-A0)

The address inputs are used to define the 3 least

significant bits of the 7-bit device address code -

1010 (A2) (A1) (A0). These pins can be con-

nected either high or low. A maximum of eight

Turbo IC 24C64 can be connected in parallel,

each with a unique device address. When these

pins are left unconnected, the device addresses

are interpreted as zero.

WRITE PROTECT (WP)

When the write protect input is connected to Vcc,

the upper quadrant of memory (1800-1FFFH) is

protected against write operations. For normal

write operation, the write protect pin should be

grounded. When this pin is left unconnected, WP

is interpreted as zero.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data

in and out of the Turbo IC 24C64. The pin is an

open-

TU24C64CP3 Related Products

	TU24C64CP3	24C64	TU24C64CS3	TU24C64CS2	TU24C64CP2
Description	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM	CMOS IC 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM

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