TTSI1K16T3TL datasheet, PDF - EEWORLD Datasheet

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TTSI1K16T3TL: Description1024-Channel, 16-Highway Time-Slot Interchanger; File Size491KB，64 Pages; ManufacturerAgere System(LSI Logic)

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1024-Channel, 16-Highway Time-Slot Interchanger

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Preliminary Data Sheet

February 1999

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

Features

Applications

Sixteen full-duplex, serial time-division multiplexed

(TDM) highways.

Full availability, nonblocking 1024-channel time/

space switch.

2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64

time slots), or 8.192 Mbits/s (128 time slots) data

rates, independently programmable per highway.

64 kbits/s granularity with optional 32 kbits/s (4-bit)

and 16 kbits/s (2-bit) subrate switching, selectable

per highway.

Low-latency mode for voice channels.

Frame integrity for wideband data applications.

Concentration highway interface (CHI) compatible

with the IOM2, GCI, K2, SLD,

MVIP

*, ST-Bus,

SC-Bus, and H.100.

Single highway clock and frame synchronization

input.

Independently programmable bit and byte offsets

with 1/4 bit resolution for all highways.

Capable of broadcasting data to the transmit high-

ways from a variety of sources including host data.

High-impedance control per time slot.

Software-compatible family of 1K, 2K, and 4K time-

slot interchangers.

Sixteen independent high-impedance indicators

(output enables) for transmit highways, allowing

external drivers.

Direct access to device registers, connection store,

and data store via microprocessor interface.

IEEE

†

1149.1 boundary scan (JTAG).

Test-pattern generation and checking for on-line

system testing (PRBS, QRSS, or user-defined

byte).

User-accessible BIST for data and connection

stores.

3.3 V power supply with 5 V tolerant I/O.

Low-power, high-density CMOS technology, and

TTL compatible switching thresholds.

144-pin TQFP package.

–40

°C

to +85

°C

operating temperature range.

Small and medium digital switch matrices.

Computer telephony integration (CTI).

Access concentrators.

PABX.

Cellular infrastructure.

ISP modem banks.

T1/E1 multiplexers.

Digital cross connects.

Digital loop carriers.

Multiport DS1/E1 service cards.

LAN/WAN gateways.

TDM highway data rate adaptation.

Description

The TTSI1K16T Time-Slot Interchanger (TSI)

switches data between 16 full-duplex, serial, time-

division multiplexed highways. The TTSI1K16T can

make any connection between 1024 input and output

time slots.

Each of the 16 transmit and 16 receive highways can

be independently programmed for data rate

(2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) and

offset. The offset can range from 0 bits to 127 bytes

and 7 3/4 bits on a 8.192 Mbits/s highway. The

TTSI1K16T can perform rate adaptation between

varying speed highways as well.

The TTSI1K16T is configured via a microprocessor

interface with a demultiplexed address and data bus.

In addition to accessing the registers and connection

store, this interface can also be used to read

received time slots and specify user data for trans-

mission.

The TTSI1K16T ensures that interchanged time slots

retain their frame integrity. Frame integrity is required

for applications that switch wideband data (i.e., ISDN

H-channels). For voice applications where low delay

is important, a low-latency mode can be selected.

MVIP

is a registered trademark of Natural Microsystems Corpo-

ration.

†

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

Preliminary Data Sheet

February 1999

Table of Contents

Contents

Page

Features .................................................................................................................................................................. 1

Applications ............................................................................................................................................................. 1

Description............................................................................................................................................................... 1

Functional Description ............................................................................................................................................. 5

Pin Information ........................................................................................................................................................ 7

Typical TSI Application .......................................................................................................................................... 13

Interchange Fabric................................................................................................................................................. 14

Small and Large TSIs ............................................................................................................................................ 15

Microprocessor Interface ....................................................................................................................................... 16

Asynchronous Mode (MM = 0)........................................................................................................................... 16

Synchronous Mode (MM = 1) ............................................................................................................................ 17

Highway Data Rate Selection................................................................................................................................ 18

Mixed-Highway Data Rates ................................................................................................................................... 19

TDM Highway Interface Timing ............................................................................................................................. 20

Virtual and Physical Frames .............................................................................................................................. 20

TDM Highway Alignment at Zero Offset ............................................................................................................ 21

TDM Highway Offsets............................................................................................................................................ 21

Reset Sequence .................................................................................................................................................... 22

Low-Latency and Frame-Integrity Modes .............................................................................................................. 23

Low Latency....................................................................................................................................................... 23

Frame Integrity................................................................................................................................................... 24

Test-Pattern Generation ........................................................................................................................................ 27

Test-Pattern Checking........................................................................................................................................... 27

Error Injection ........................................................................................................................................................ 28

Error Checking....................................................................................................................................................... 28

JTAG Boundary-Scan Specification ...................................................................................................................... 29

Principle of the Boundary Scan.......................................................................................................................... 29

Test Access Port Controller ............................................................................................................................... 30

Instruction Register ............................................................................................................................................ 32

Boundary-Scan Register.................................................................................................................................... 33

BYPASS Register .............................................................................................................................................. 33

IDCODE Register............................................................................................................................................... 33

3-State Procedures ............................................................................................................................................ 33

Register Architecture ............................................................................................................................................. 34

Configuration Register Architecture....................................................................................................................... 36

Transmit Highway 3-State Options .................................................................................................................... 49

Data Store Memory ............................................................................................................................................... 50

Connection Store Memory..................................................................................................................................... 50

Absolute Maximum Ratings................................................................................................................................... 53

Operating Conditions............................................................................................................................................. 53

Handling Precautions ............................................................................................................................................ 53

Electrical Characteristics ....................................................................................................................................... 54

Timing Characteristics ........................................................................................................................................... 54

Outline Diagram..................................................................................................................................................... 61

144-Pin TQFP .................................................................................................................................................... 61

Ordering Information.............................................................................................................................................. 62

DS99-177PDH Replaces DS98-290TIC to Incorporate the Following Updates .................................................... 62

Lucent Technologies Inc.

Preliminary Data Sheet

February 1999

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

List of Figures

Figures

Page

Figure 1. Block Diagram of the TTSI1K16T .............................................................................................................6

Figure 2. 144-Pin TQFP Pin Assignment (Top View)...............................................................................................7

Figure 3. A Typical TSI Application ........................................................................................................................13

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................15

Figure 5. Asynchronous Read................................................................................................................................16

Figure 6. Asynchronous Write................................................................................................................................16

Figure 7. Synchronous Read .................................................................................................................................17

Figure 8. Synchronous Write..................................................................................................................................17

Figure 9. Mixed-Highway Data Rates ....................................................................................................................19

Figure 10. Virtual and Physical Frames .................................................................................................................20

Figure 11. Synchronization to FSYNC ...................................................................................................................21

Figure 12. Highway Offsets ....................................................................................................................................22

Figure 13. Mixed Low-Latency and Frame-Integrity Modes ...................................................................................26

Figure 14. Block Diagram of the TTSI1K16T's Boundary-Scan Test Logic ...........................................................29

Figure 15. BS TAP Controller State Diagram.........................................................................................................30

Figure 16. Asynchronous Read Cycle Timing Using DT Handshake.....................................................................55

Figure 17. Asynchronous Write Cycle Timing Using DT Handshake .....................................................................55

Figure 18. Asynchronous Read Cycle Timing Using Only CS ...............................................................................56

Figure 19. Asynchronous Write Cycle Timing Using Only CS ...............................................................................56

Figure 20. Synchronous Read Cycle Timing..........................................................................................................57

Figure 21. Synchronous Write Cycle Timing ..........................................................................................................57

Figure 22. TDM Highway Timing............................................................................................................................59

Figure 23. JTAG Interface Timing ..........................................................................................................................60

Lucent Technologies Inc.

TTSI2K32T

1024-Channel, 16-Highway Time-Slot Interchanger

Preliminary Data Sheet

February 1999

List of Tables

Tables

Page

Table 1. Data Rate and Switch Size Examples ....................................................................................................... 5

Table 2. Pin Assignments for a 144-Pin TQFP—Pin Number Order....................................................................... 8

Table 3. Pin Assignments for a 144-Pin TQFP—Signal Name Order ..................................................................... 9

Table 4. TTSI1K16T Pin Descriptions ................................................................................................................... 10

Table 5. The TSI Family ........................................................................................................................................ 15

Table 6. Rx Highway Data Rate Options............................................................................................................... 18

Table 7. Tx Highway Data Rate Options ............................................................................................................... 18

Table 8. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets) ............................. 23

Table 9. Offset Difference and Its Effect on Frame for Transmission.................................................................... 25

Table 10. Offset Difference Boundaries ................................................................................................................ 25

Table 11. TAP Controller States in the Data Register Branch............................................................................... 31

Table 12. TAP Controller States in the Instruction Register Branch...................................................................... 31

Table 13. TTSI1K16T’s Boundary-Scan Instructions ............................................................................................ 32

Table 14. TTSI1K16T Register Summary ............................................................................................................. 34

Table 15. General Command Register (0x00) ...................................................................................................... 36

Table 16. Software Reset Register (0x01) ............................................................................................................ 37

Table 17. BIST Command Register (0x02) ........................................................................................................... 37

Table 18. Idle Code 1 Register (0x03)................................................................................................................... 38

Table 19. Idle Code 2 Register (0x04)................................................................................................................... 38

Table 20. Idle Code 3 Register (0x05)................................................................................................................... 38

Table 21. Global Interrupt Mask Register (0x06)................................................................................................... 38

Table 22. Interrupt Status Register (0x07) ............................................................................................................ 39

Table 23. Interrupt Mask Register (0x08) .............................................................................................................. 40

Table 24. Test Command Register (0x09) ............................................................................................................ 41

Table 25. Test-Pattern Style Register (0x0A)........................................................................................................ 42

Table 26. Test-Pattern Checker Highway Register (0x0B).................................................................................... 43

Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C) ....................................................................... 43

Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D) ....................................................................... 43

Table 29. Test-Pattern Checker Data Register (0x0E).......................................................................................... 43

Table 30. Test-Pattern Error Injection Register (0x0F).......................................................................................... 43

Table 31. Test-Pattern Error Counter (Byte 0) (0x10) ........................................................................................... 44

Table 32. Test-Pattern Error Counter (Byte 1) (0x11) ........................................................................................... 44

Table 33. Test-Pattern Generator Data Register (0x12) ....................................................................................... 44

Table 34. Version Register (0x13)......................................................................................................................... 44

Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i) ......................................................... 45

Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i) ......................................................... 46

Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i) ......................................................... 46

Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i) .......................................................... 47

Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i) .......................................................... 48

Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i) .......................................................... 48

Table 41. Transmit Highway 3-State Options........................................................................................................ 49

Table 42. Address Scheme for Data Store Memory ............................................................................................. 50

Table 43. Address Scheme for Connection Store Memory .................................................................................. 50

Table 44. Connection Store Memory (Byte 0) ....................................................................................................... 51

Table 45. Connection Store Memory (Byte 1) ....................................................................................................... 51

Table 46. Clock Specifications .............................................................................................................................. 54

Table 47. Asynchronous Read and Write Interface Timing Using DT Handshake................................................ 55

Table 48. Asynchronous Microprocessor Interface Timing Using Only CS .......................................................... 56

Table 49. Synchronous Microprocessor Interface Timing ..................................................................................... 58

Table 50. TDM Highway Timing ............................................................................................................................ 59

Table 51. JTAG Interface Timing........................................................................................................................... 60

Lucent Technologies Inc.

TTSI1K16T3TL Related Products

	TTSI1K16T3TL	TTSI1K16T
Description	1024-Channel, 16-Highway Time-Slot Interchanger	1024-Channel, 16-Highway Time-Slot Interchanger

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