74HCT377D datasheet, PDF - EEWORLD Datasheet

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74HCT377D: DescriptionIC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SO-20, FF/Latch; Categorylogic logic; File Size136KB，19 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74HCT377D Overview

IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SO-20, FF/Latch

74HCT377D Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	PLASTIC, SO-20
Contacts	20
Reach Compliance Code	unknown
Other features	WITH HOLD MODE
series	HCT
JESD-30 code	R-PDSO-G20
length	12.8 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	22000000 Hz
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
propagation delay (tpd)	48 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL/PALLADIUM/GOLD (NI/PD/AU)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	7.5 mm
minfmax	60 MHz

74HCT377D Preview

74HC377; 74HCT377

Octal D-type flip-flop with data enable; positive-edge trigger

Rev. 3 — 25 September 2013

Product data sheet

1. General description

The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device

features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume

the state of their corresponding Dn inputs that meet the set-up and hold time requirements

on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to

the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that

enable the use of current limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits



Common clock and master reset

Eight positive edge-triggered D-type flip-flops

Complies with JEDEC standard no. 7A

Input levels:



For 74HC377: CMOS level



For 74HCT377: TTL level



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V.



Multiple package options



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74HC377N

74HCT377N

74HC377D

74HCT377D

74HC377DB

74HCT377DB

74HC377PW

74HCT377PW

40 C

to +85

C

40 C

to +85

C

SSOP20

plastic shrink small outline package; 20 leads; body width

5.3 mm

SOT339-1

SOT360-1

40 C

to +85

C

SO20

plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

40 C

to +85

C

DIP20

Description

plastic dual in-line package; 20 leads (300 mil)

Version

SOT146-1

Type number

TSSOP20 plastic thin shrink small outline package; 20 leads; body

width 4.4 mm

NXP Semiconductors

74HC377; 74HCT377

Octal D-type flip-flop with data enable; positive-edge trigger

4. Functional diagram

FF1

FF8

OUTPUTS

11 CP

mna606

Fig 1.

Functional diagram

mna918

1C2

mna919

Fig 2.

Logic symbol

Fig 3.

IEC logic symbol

74HC_HCT377

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

2 of 19

NXP Semiconductors

74HC377; 74HCT377

Octal D-type flip-flop with data enable; positive-edge trigger

FF1

FF2

FF3

FF4

FF5

FF6

FF7

FF8

mna610

Fig 4.

Logic diagram

74HC_HCT377

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

3 of 19

NXP Semiconductors

74HC377; 74HCT377

Octal D-type flip-flop with data enable; positive-edge trigger

5. Pinning information

5.1 Pinning

20 V

19 Q7

18 D7

17 D6

377

16 Q6

15 Q5

14 D5

13 D4

12 Q4

11 CP

mna917

GND 10

Fig 5.

Pin configuration

5.2 Pin description

Table 2.

Symbol

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

D0, D1, D2, D3, D4, D5, D6, D7

GND

Pin description

2, 5, 6, 9, 12, 15, 16, 19

3, 4, 7, 8, 13, 14, 17, 18

Description

data enable input (active LOW)

flip-flop output

data input

ground (0 V)

clock input (LOW-to-HIGH, edge triggered)

supply voltage

6. Functional description

Table 3.

Function table

[1]

Inputs

load “1”

load “0”

hold (do nothing)



[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;



= LOW-to-HIGH clock transition.

Operating modes

Outputs

no change

74HC_HCT377

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

4 of 19

NXP Semiconductors

74HC377; 74HCT377

Octal D-type flip-flop with data enable; positive-edge trigger

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol

GND

stg

tot

Parameter

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

amb

40 C

to +125

C

DIP20 package

SO20, SSOP20, TSSOP20

[1]

[2]

[3]

[2]

[3]

Conditions

0.5

V or V

> V

+ 0.5 V

0.5

V or V

> V

+ 0.5 V

0.5

V < V

< V

+ 0.5 V

[1]

Min

0.5

50

65

Max

20

25

+150

750

500

Unit

C

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

For DIP20 package: above 70

C

the value of P

tot

derates linearly with 12 mW/K.

For SO20 package: above 70

C

the value of P

tot

derates linearly with 8 mW/K.

For SSOP20 and TSSOP20 packages: above 60

C

the value of P

tot

derates linearly with 5.5 mW/K.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

amb

t/V

supply voltage

input voltage

output voltage

ambient temperature

input transition rise and fall rate

= 2.0 V

= 4.5 V

= 6.0 V

Conditions

Min

2.0

40

74HC377

Typ

5.0

1.67

Max

6.0

+125

625

139

Min

4.5

40

74HCT377

Typ

5.0

1.67

Max

5.5

+125

139

C

ns/V

Unit

74HC_HCT377

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

5 of 19

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74HCT377D Related Products

	74HCT377D	74HC377N
Description	IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SO-20, FF/Latch	IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20, FF/Latch
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	SOIC	DIP
package instruction	PLASTIC, SO-20	DIP, DIP20,.3
Contacts	20	20
Reach Compliance Code	unknown	unknown
Other features	WITH HOLD MODE	WITH HOLD MODE
series	HCT	HC/UH
JESD-30 code	R-PDSO-G20	R-PDIP-T20
length	12.8 mm	26.73 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	22000000 Hz	24000000 Hz
MaximumI(ol)	0.004 A	0.004 A
Number of digits	8	8
Number of functions	1	1
Number of terminals	20	20
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP
Encapsulate equivalent code	SOP20,.3	DIP20,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE
Peak Reflow Temperature (Celsius)	260	NOT SPECIFIED
power supply	5 V	2/6 V
propagation delay (tpd)	48 ns	48 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.65 mm	4.2 mm
Maximum supply voltage (Vsup)	5.5 V	6 V
Minimum supply voltage (Vsup)	4.5 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL/PALLADIUM/GOLD (NI/PD/AU)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	NOT SPECIFIED
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	7.5 mm	7.62 mm
minfmax	60 MHz	60 MHz

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