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WS1M8V-45CM

Description
Standard SRAM, 1MX8, 45ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32
Categorystorage    storage   
File Size134KB,5 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

WS1M8V-45CM Overview

Standard SRAM, 1MX8, 45ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32

WS1M8V-45CM Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instruction0.600 INCH, CERAMIC, DIP-32
Reach Compliance Codeunknown
Maximum access time45 ns
JESD-30 codeR-CDIP-T32
memory density8388608 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize1MX8
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal locationDUAL
WS1M8V-XCX
2x512Kx8 DUALITHIC™ SRAM
PIN CONFIGURATION FOR WS1M8V-XCX
32 DIP
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
ADVANCED*
FEATURES
s
Access Times 17, 20, 25, 35, 45, 55ns
s
Evolutionary, Corner Power/Ground Pinout
s
Packaging:
• 32 pin, Hermetic Ceramic DIP (Package 300)
s
Organized as two banks of 512Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
3.3V Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
s
Output Enable Internally tied to GND.
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
3
SRAM DUALITHICS
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
1-2
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Write Enable
+3.3V Power Supply
Ground
BLOCK DIAGRAM
I/O
0-7
WE
A
0-18
512K x 8
512K x 8
CS
1
(1)
CS
2
(1)
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 512Kx8 of the
device. CS
1
and CS
2
must not be enabled at the same time.
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
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