ADVANCE INFORMATION
MICRONAS
DDP 3310B
Display and Deflection
Processor
Edition July 9, 1999
6251-464-1AI
MICRONAS
DDP 3310B
Contents
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34
Section
1.
1.1.
1.2.
1.3.
2.
2.1.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.6.
2.1.7.
2.1.8.
2.1.9.
2.1.10.
2.1.11.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
2.3.6.
2.3.7.
2.3.8.
2.3.9.
2.3.10.
2.3.11.
2.3.12.
2.3.13.
3.
3.1.
3.2.
3.3.
3.3.1.
Title
Introduction
Main Features
System Architecture
System Application
Functional Description
Display Part
Input Interface
Horizontal Scaler
Luma Processing
Dynamic Peaking
Soft Limiter
Chroma Input
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix and Digital RGB Processing
Picture Frame Generator
Scan Velocity Modulation
Analog Back-End
Analog RGB Insertion
Half-Contrast Control
Fast-Blank Monitor
CRT Measurement and Control
Average Beam Current Limiter
Synchronization and Deflection
Deflection Processing
Security Unit for H-Drive
Soft Start/Stop of Horizontal Drive
Horizontal Phase Adjustment
Vertical Synchronization
Vertical and East/West Deflection
Vertical Zoom
EHT Compensation
Protection Circuitry
Display Frequency Doubling
General-purpose D/A Converter
Clock and Reset
Reset and Power-On
Serial Interface
I
2
C-Bus Interface
I
2
C Control and Status Registers
XDFP Control and Status Registers
Scaler Adjustment
ADVANCE INFORMATION
2
Micronas
ADVANCE INFORMATION
DDP 3310B
Contents, continued
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Section
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.4.1.
4.6.4.2.
4.6.4.3.
4.6.4.4.
4.6.4.5.
4.6.4.6.
4.6.4.7.
4.6.4.8.
4.6.4.9.
4.6.4.10.
4.6.4.11.
4.6.4.12.
4.6.4.13.
4.6.4.14.
4.6.4.15.
4.6.4.16.
4.6.4.17.
4.6.4.18.
4.6.4.19.
5.
6.
Title
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Description
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Crystal Characteristics
Characteristics
General Characteristics
Line-locked Clock Inputs: LLC1, LLC2
Luma, Chroma Inputs
Reset Input, Test Input
Half-Contrast Input
I
2
C-Bus Interface
Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Horizontal Flyback Input
FIFO Control Signals
PWM Outputs
Horizontal Drive Output
Vertical Protection Input
Horizontal Safety Input
Vertical and East/West D/A Converter Output
Sense A/D Converter Input
Analog RGB and Fast-Blank Inputs
Analog RGB Outputs, D/A Converters
Scan Velocity Modulation Output
DAC Reference, Beam Current Safety
Application Circuit
Data Sheet History
Micronas
3
DDP 3310B
Display and Deflection Processor
1. Introduction
The DDP 3310B is a single-chip digital Display and
Deflection Processor designed for high-quality back-
end applications in 100/120-Hz TV sets with 4:3- or
16:9 picture tubes. The IC can be combined with mem-
bers of the DIGIT 3000 IC family (VPC 32xx,
TPU 3040), or it can be used with third-party products.
The IC contains the entire digital video component and
deflection processing and all analog interface compo-
nents.
Deflection processing
ADVANCE INFORMATION
– scan velocity modulation output
– high-performance H/V deflection
– EHT compensation for vertical / East/West
– soft start/stop of H-Drive
– vertical angle and bow
– differential vertical output
– vertical zoom via deflection
– horizontal and vertical protection circuit
– adjustable horizontal frequency for VGA/SVGA dis-
play
Miscellaneous
– selectable 4:1:1/4:2:2 YC
r
C
b
input
– selectable 27/32-MHz line-locked clock input
– crystal oscillator for horizontal protection
– automatic picture tube adjustment (cutoff, white-
drive)
– single 5-V power supply
– hardware for simple 50/60-Hz to 100/120-Hz con-
version (display frequency doubling)
– two I
2
C-controlled PWM outputs
– beam current limiter
1.1. Main Features
Video processing
– linear horizontal scaling (0.25 … 4)
– non-linear horizontal scaling “panoramavision”
– dynamic peaking
– soft limiter (gamma correction)
– color transient improvement
– programmable RGB matrix
– picture frame generator
– two analog RGB/Fast-Blank inputs
YC
r
C
b
4:2:2/4:1:1
Line-locked
Clock
27/32 MHz
Hori-
zontal
Scaler
Clock
Gen.
I
2
C
Inter-
face
Y Features
C Features
Digital
RGB
Matrix
Picture
Frame
Generator
3 x DAC
(10 Bit)
Tube Control
Analog
RGB
Switch
Scan
Velocity
Modulation
RGB
Out
2xRGB/FB
In
SVM
SDA/SCL
PWM
Measure-
ment
ADC
H/V
Deflection
Security
Unit
DACs
Display
Frequency
Doubling
HDrive
V & E/W
FIFO
Controlling
PWM
1&2
Fig. 1–1:
Block diagram of the DDP 3310B
Sense
Input
2H / 2V
(1H/1V)
HFlyback
4
Micronas
ADVANCE INFORMATION
DDP 3310B
ation is derived from a single 20.25-MHz crystal. An
optional adaptive 2H/4H comb filter (VPC 32xx) per-
forms Y/C separation for PAL and NTSC and all of their
substandards.
The VPC 32xxD and the CIP 3250A provide a high-
quality analog RGB interface with character insertion
capability. This allows appropriate processing of exter-
nal sources such as MPEG 2 set-top boxes in trans-
parent (4:2:2) quality. Furthermore, it translates RGB/
Fast-Blank signals to the common digital video bus
and makes those signals available for 100-Hz process-
ing. In some European countries (Italy), this feature is
mandatory.
The IP indicates memory-based image processing,
such as scan rate conversion, vertical processing
(Zoom), or PAL+ reconstruction.
Examples:
– Europe: 15 kHz/ 50 Hz
→
32 kHz/100 Hz interlaced
– US: 15 kHz/60 Hz
→
31 kHz/120 Hz non-interlaced
Note:
The DDP 3310B and the VPC 32xx families
support memory-based applications through line-
locked clocks, syncs, and data. The CIP 3250A may
run either with the native DIGIT3000 clock but also
with a line-locked clock system.
1.2. System Architecture
The DDP 3310B is a mixed-signal IC containing the
entire digital video component processing such as
chroma transient improvement (CTI), adaptive luma
peaking, and a non-linear ‘Panorama’ aspect ratio con-
version. All deflection related signals can be adapted
to different scan rates. The analog section contains all
analog interface components and an ADC, to compen-
sate long term changes of the picture tube parameters
and extreme high-tension effects. Fig. 1–1 shows the
block diagram of the single-chip Display and Deflection
Processor.
1.3. System Application
Fig. 1–2 depicts several DDP applications. Since the
DDP functions as a video back-end, it must be comple-
mented with additional functionality to form a complete
TV set.
The VPC 32xx family processes all worldwide analog
video signals (including the European PALplus) and
allows non-linear Panorama aspect ratio conversion.
Thus, 4:3 and 16:9 systems can easily be configured
by software. The aspect ratio scaling is also used as a
sample rate converter to provide a line-locked digital
component output bus (YC
r
C
b
) compliant to ITU-R-601.
All video processing and line-locked clock/data gener-
Scan Velocity Modulation
Fast Blank Mixing
RGB Saturation
Comb Filter
16:9 Video
VPC 32xxD
CVBS
RGB
VPC
32xx
CIP
3250A
IP
DDP
3310B
H/V
Defl.
RGB
CVBS
VPC
32xx
FIFO
DDP
3310B
H/V
Defl.
✔
✔
✔
✔
✔
PAL+
100 Hz
RGB
✔
✔
✔
Fig. 1–2:
DDP 3310B applications
Micronas
IP
5
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