Preliminary W83196S-14
100 MHZ CLOCK FOR BX CHIPSET (2 CHIP)
1. GENERAL DESCRIPTION
The W83196S-14 is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor. Twelve different frequency of CPU, and PCI clocks are externally selectable
with smooth transitions.
The W83196S-14 provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and choose the 0.5% center type spread spectrum to reduce EMI.
The W83196S-14 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1V/nS slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1V/nS slew rate into 20 pF loads as maintaining 50
±5%
duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V/nS
slew rate.
2. FEATURES
•
Supports Pentium II CPUs with I C
•
12 sets of CPU frequencies selection
•
2 CPU clocks (one free running CPU clock)
•
7 PCI synchronous clocks(one free running PCI clock)
•
Optional single or mixed supply:
2
(V
DD
R = V
DD
Core = V
DD
P = V
DD
4 = 3.3V
±5%)
(V
DD
A = V
DD
C = 2.5V
±5%)
•
Skew form CPU to PCI clock 1.5 to 4.0 nS, CPU leads.
•
CPU clock jitter less than 200 pS
•
PCI_F, PCI1: 6 clock skew less than 500 pS
•
Smooth frequency switch with selections from 66.8 MHz to 150 MHz CPU
•
I C 2-Wire serial interface and I C read back
•
±0.5%
center type spread spectrum function to reduce EMI
•
Programmable registers to enable/stop each output and select modes
2
2
(mode as Tri-state or Normal )
•
MODE pin for power management
•
48 MHz for USB
•
24 MHz for super I/O
•
Packaged in 28-pin SOP
-1-
Publication Release Date: March 1999
Revision A1
Preliminary W83196S-14
3. BLOCK DIAGRAM
VDDR
X1
X2
REF2X
XTAL
OSC
VDDA
IOAPIC
VDDC
SEL100/66#
Spread
Spectrum
÷2/3/4
PLL1
STOP
VDDC
VDDP
PCI
clock
Divder
STOP
6
CPUCLK_F
CPUCLK1
SEL48*
MODE*
Latch
PCICLK(1:6)
PCICLK_F
CPU_STOP#
PCI_STOP#
SDATA*
SCLK*
Contro
Logic
Config.
Reg.
PLL2
VDDP
VDD4
48MHz
24/48MHz
VDD4
4. PIN CONFIGURATION
Xin
Xout
VssP
PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDP
PCI_STOP#/PCICLK5
CPU_STOP#/PCICLK6
VDD4
48MHz/Mode*
24/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VssR
REF2X/SEL48*
VDDR
VDDA
IOAPIC
VDDC
CPUCLK_F
CPUCLK1
VDDCore
VssC
SDATA
SDCLK
SEL100/66#
Vss4
-2-
Preliminary W83196S-14
5. PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Low active
* - Internal 250kΩ pull-up
5.1 Crystal I/O
SYMBOL
Xin
Xout
PIN
1
2
I/O
IN
FUNCTION
Crystal input with internal loading capacitors and feedback
resistors.
OUT Crystal output at 14.318 MHz nominally.
5.2 CPU, PCI Clock Outputs
SYMBOL
CPUCLK_F
CPUCLK1
PCICLK [ 1:4 ]
PCICLK_F
PCICLK5/
PCI_STOP#
PCICLK6/
CPU_STOP#
11
I/O
10
I/O
If Mode* =1 (default), then this pin is a PCICLK5 buffered
output of the crystal. If Mode* = 0 , then this pin is
PCI_STOP# input used in power management mode for
synchronously stopping the all CPU clocks.
If Mode* = 1 (default), then this pin is a PCICLK6 clock
output. If Mode* = 0 , then this pin is CPU_STOP # and
used in power management mode for synchronously
stopping the all PCI clocks.
4, 5, 6, 7, 8
PIN
22, 21
I/O
FUNCTION
OUT Low skew (<250 pS) clock outputs for host frequencies
such as CPU, Chipset and Cache. V
DD
C is the supply
voltage for these outputs.
OUT Low skew (<250 pS) PCI clock outputs.
5.3 I2C Control Interface
SYMBOL
SDATA*
SDCLK*
PIN
18
17
I/O
I/O
IN
FUNCTION
Serial data of I
2
C 2-wire control interface
Serial clock of I
2
C 2-wire control interface
-3-
Publication Release Date: March 1999
Revision A1
Preliminary W83196S-14
5.4 Fixed Frequency Outputs
SYMBOL
SEL100/66#
IOAPIC
REF2X / SEL48*
PIN
16
24
27
I/O
IN
O
I/O
FUNCTION
CPU clock frequency select pin.
Provides 14.318 fixed frequency.
Internal 250kΩ pull-up.
Latched input for SEL48* at initial power up.
SEL48* = 1 , pin14 is 24 MHz
SEL48* = 0 , pin14 is 48 MHz
Reference clock during normal operation.
24/48MHz
48MHz/Mode*
14
13
O
I/O
Frequency is set by the state of pin 27 on power up.
Internal 250kΩ pull-up.
48 MHz output for USB during normal operation.
Latched input for Mode* at initial power up. Mode* = 0 ,
then pin10 is PCI_STOP#, and pin11 is CPU_STOP#.
Mode* = 1.(default), pin10 is PCICLK5 and pin11 is
PCLCLK6.
5.5 Power Pins
SYMBOL
V
DD
Core
V
DD
P
V
DD
A
V
DD
C
V
DD
4
V
DD
R
VssC, VssR, Vss4,
VssP
PIN
20
9
25
23
12
26
FUNCTION
Power supply for core logic and PLL circuitry. Connect to 3.3V
supply.
Power supply for PCICLK_F and PCICLK 1:6. Connect to 3.3V
supply.
Power supply for IOAPIC output, Connect to 2.5V supply
Power supply for CPUCLK _F and CPUCLK1. Connect to 2.5V
supply.
Power supply for 48mhz USB clock . Connect to 3.3V supply.
Power supply for 14.318mhz ISA clock . Connect to 3.3V supply.
3, 15, 19, Circuit Ground.
28
6. FREQUENCY SELECTION
SEL100/66#
1
0
CPUCLK_F, CPUCLK1
100 MHz
66.8 MHz
PCI
33.3 MHz
33.3 MHz
-4-
Preliminary W83196S-14
7. FUNCTIONAL DESCRIPTION
7.1 Power Mamagement Functions
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCOs to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE = 0, pins 10 and 11 are inputs (PCI_STOP#), (CPU_STOP#),
when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2-
wire serial control interface and one of these pins indicate that it should be enabled.
The W83196S-14 may be disabled in the low state according to the following table in order to reduce
power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
0
0
1
1
PCI_STOP#
0
1
0
1
CPUCLK1
LOW
LOW
RUNNING
RUNNING
PCICLK1:4
LOW
RUNNING
LOW
RUNNING
CPUCLK_F&
PCICLK_F
RUNNING
RUNNING
RUNNING
RUNNING
XTAL & VCOs
RUNNING
RUNNING
RUNNING
RUNNING
7.2 2-Wire I
2
C Control Interface
The clock generator is a slave I
2
C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83196S-14 initializes with default register settings, and then it is optional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high
transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is
always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101
0010], command code checking [0000 0000], and byte count checking. After successful reception of
each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller
can start to write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
-5-
Publication Release Date: March 1999
Revision A1
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