MT48LCM32B2P datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > MT48LCM32B2P

Preview

MT48LCM32B2P: DescriptionSDR SDRAM MT48LC2M32B2 â 512K x 32 x 4 Banks; File Size4MB，80 Pages; ManufacturerMicron; Websitehttp://www.micron.com/

Download Datasheet Compare View All

MT48LCM32B2P Overview

SDR SDRAM MT48LC2M32B2 â 512K x 32 x 4 Banks

Preview

Download Datasheet

View All

64Mb: x32 SDRAM

Features

SDR SDRAM

MT48LC2M32B2 – 512K x 32 x 4 Banks

Features

• PC100-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 4096-cycle refresh

(commercial and industrial)

– 16ms, 4096-cycle refresh

(automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Options

• Configuration

– 2 Meg x 32 (512K x 32 x 4 banks)

• Plastic package – OCPL

– 86-pin TSOP II (400 mil) standard

– 86-pin TSOP II (400 mil) Pb-free

– 90-ball VFBGA (8mm x 13mm) Pb-

free

• Timing – cycle time

– 5ns (200 MHz)

– 5.5ns (183 MHz)

– 6ns (167 MHz)

– 7ns (143 MHz)

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Revision

Notes:

Off-center parting line.

Available only on revision G.

Available only on revision J.

Contact Micron for availability.

Marking

2M32B2

-5

-55

-6A

-6

-7

None

:G/:J

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-5

-55

-6A

-6

-7

Clock

Frequency (MHz)

200

183

167

143

Target

RCD-

RP-CL

3-3-3

RCD

(ns)

CL (ns)

16.5

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ....................................................................................................... 9

Package Dimensions ....................................................................................................................................... 12

Temperature and Thermal Impedance ............................................................................................................ 14

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 19

Electrical Specifications – AC Operating Conditions ......................................................................................... 21

Functional Description ................................................................................................................................... 24

Commands .................................................................................................................................................... 25

COMMAND INHIBIT .................................................................................................................................. 25

NO OPERATION (NOP) ............................................................................................................................... 26

LOAD MODE REGISTER (LMR) ................................................................................................................... 26

ACTIVE ...................................................................................................................................................... 26

READ ......................................................................................................................................................... 27

WRITE ....................................................................................................................................................... 28

PRECHARGE .............................................................................................................................................. 29

BURST TERMINATE ................................................................................................................................... 29

REFRESH ................................................................................................................................................... 30

AUTO REFRESH ..................................................................................................................................... 30

SELF REFRESH ....................................................................................................................................... 30

Truth Tables ................................................................................................................................................... 31

Initialization .................................................................................................................................................. 36

Mode Register ................................................................................................................................................ 38

Burst Length .............................................................................................................................................. 40

Burst Type .................................................................................................................................................. 40

CAS Latency ............................................................................................................................................... 42

Operating Mode ......................................................................................................................................... 42

Write Burst Mode ....................................................................................................................................... 42

Bank/Row Activation ...................................................................................................................................... 43

READ Operation ............................................................................................................................................. 44

WRITE Operation ........................................................................................................................................... 53

Burst Read/Single Write .............................................................................................................................. 60

PRECHARGE Operation .................................................................................................................................. 61

Auto Precharge ........................................................................................................................................... 61

AUTO REFRESH Operation ............................................................................................................................. 73

SELF REFRESH Operation ............................................................................................................................... 75

Power-Down .................................................................................................................................................. 77

Clock Suspend ............................................................................................................................................... 78

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

List of Figures

Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8

Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9

Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 13

Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15

Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16

Figure 8: ACTIVE Command .......................................................................................................................... 26

Figure 9: READ Command ............................................................................................................................. 27

Figure 10: WRITE Command ......................................................................................................................... 28

Figure 11: PRECHARGE Command ................................................................................................................ 29

Figure 12: Initialize and Load Mode Register .................................................................................................. 37

Figure 13: Mode Register Definition ............................................................................................................... 39

Figure 14: CAS Latency .................................................................................................................................. 42

Figure 15: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 43

Figure 16: Consecutive READ Bursts .............................................................................................................. 45

Figure 17: Random READ Accesses ................................................................................................................ 46

Figure 18: READ-to-WRITE ............................................................................................................................ 47

Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48

Figure 20: READ-to-PRECHARGE .................................................................................................................. 48

Figure 21: Terminating a READ Burst ............................................................................................................. 49

Figure 22: Alternating Bank Read Accesses ..................................................................................................... 50

Figure 23: READ Continuous Page Burst ......................................................................................................... 51

Figure 24: READ – DQM Operation ................................................................................................................ 52

Figure 25: WRITE Burst ................................................................................................................................. 53

Figure 26: WRITE-to-WRITE .......................................................................................................................... 54

Figure 27: Random WRITE Cycles .................................................................................................................. 55

Figure 28: WRITE-to-READ ............................................................................................................................ 55

Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 56

Figure 30: Terminating a WRITE Burst ............................................................................................................ 57

Figure 31: Alternating Bank Write Accesses ..................................................................................................... 58

Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 59

Figure 33: WRITE – DQM Operation ............................................................................................................... 60

Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 62

Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63

Figure 36: READ With Auto Precharge ............................................................................................................ 64

Figure 37: READ Without Auto Precharge ....................................................................................................... 65

Figure 38: Single READ With Auto Precharge .................................................................................................. 66

Figure 39: Single READ Without Auto Precharge ............................................................................................. 67

Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68

Figure 42: WRITE With Auto Precharge ........................................................................................................... 69

Figure 43: WRITE Without Auto Precharge ..................................................................................................... 70

Figure 44: Single WRITE With Auto Precharge ................................................................................................. 71

Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 72

Figure 46: Auto Refresh Mode ........................................................................................................................ 74

Figure 47: Self Refresh Mode .......................................................................................................................... 76

Figure 48: Power-Down Mode ........................................................................................................................ 77

Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 78

Figure 50: Clock Suspend During READ Burst ................................................................................................. 79

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT48LCM32B2P Related Products

	MT48LCM32B2P	MT48LC2M32B2TG-7ITG	MT48LC2M3B2B51
Description	SDR SDRAM MT48LC2M32B2 â 512K x 32 x 4 Banks	SDR SDRAM MT48LC2M32B2 â 512K x 32 x 4 Banks	SDR SDRAM MT48LC2M32B2 â 512K x 32 x 4 Banks

Recommended Resources

Simple phone code lock circuit

M708 (TV) infrared remote control transmitter circuit

Integral (quadrature) detection circuit for light-emitting diodes

Slow start integrated regulated power supply circuit

High output voltage integrated regulated power supply composed of CW137

Will the interrupt of P1 port conflict?: The P1 port has enabled two interrupts, P1.4 and P1.7, but it is found that after the rising edge interrupt of P1.7, the program no longer responds to the interrupt of P1.4. It can only continue to re...; liuxuan163 Microcontroller MCU

Ask for the final project topic: I am a senior student, and I am worried about the topic of my graduation project. I hope you seniors can help me find a topic for my graduation project. My major is electronic information engineering,...; Koutian Analog electronics

Problems encountered when posting PNG on WINCE: The system is WINCE6.0 and uses CXIMAGE texturesBut sometimes the following situation occurs, it seems that there is a problem with transparency processinghttp://img9.uploadhouse.com/fileuploads/16293...; zazard Embedded System

Why do single-power-supply circuits basically use rail-to-rail op amps?: Why do single-power-supply circuits basically use rail-to-rail op amps?...; JFET Analogue and Mixed Signal

Register for WEBENCH easily and enjoy wonderful gifts! (The event has ended, waiting for TI review, and the award ceremony is in progress): Event page >> WEBENCH Design Contest , register for TI WEBENCH and enjoy wonderful gifts! Event time: September 12, 2013 - October 12, 2013 How to participate: 1. Please log in to my.ti.com to registe...; EEWORLD社区 Analogue and Mixed Signal

Seek solutions to channel (DEFAULT_CHANLIST) conflicts in practical applications.: Deliver finished products to users for networking implementationFound that the channel (DEFAULT_CHANLIST) is already occupiedThe current solution is to modify the DEFAULT_CHANLIST definition and re-pr...; 高兴就好 RF/Wirelessly

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components