CYW137OXC datasheet, PDF - EEWORLD Datasheet

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CYW137OXC: DescriptionProcessor Specific Clock Generator, 100MHz, CMOS, PDSO28, 5.30 MM, LEAD FREE, SSOP-28; CategoryThe embedded processor and controller Microcontrollers and processors; File Size128KB，8 Pages; ManufacturerSilicon Laboratories Inc

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CYW137OXC Overview

Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 5.30 MM, LEAD FREE, SSOP-28

CYW137OXC Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	28
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	ALSO OPERATES 2.5V SUPPLY VOLTAGE
JESD-30 code	R-PDSO-G28
length	10.2 mm
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	100 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Master clock/crystal nominal frequency	14.318 MHz
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	5.3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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W137

FTG for Mobile 440BX & Transmeta’s Crusoe CPU

Features

• Maximized EMI suppression using Cypress’s Spread

Spectrum Technology

• Two copies of CPU output

• Six copies of PCI output (Synchronous w/CPU output)

• One 48-MHz output for USB support

• One selectable 24 /48 MHz output

• Two Buffered copies of 14.318 MHz input reference

signal

• Supports 100 MHz or 66 MHz CPU operation

• Power management control input pins

• Available in 28-pin SSOP (209 mils) and 28-pin TSSO

(173 mils)

• SS function can be disabled

• See W40S11-02 for 2 SDRAM DIMM support

CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps

PCI_F, PCI1:5 Output to Output Skew:....................... 500 ps

PCI_F, PCI1:5 Cycle to Cycle Jitter: .......................... 250 ps

CPU to PCI Output Skew:................1.5–4.0 ns (CPU Leads)

Output Duty Cycle:..................................................... 45/55%

PCI_F, PCI Edge Rate: .............................................. >1 V/ns

CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#,

PWR_DWN# all have a 250-kW pull-up resistor.

Table 1. Pin Selectable Frequency

SEL100/66#

0/1

CPU

Hi-Z

66.6 MHz

100 MHz

PCI

Hi-Z

33.3

Spread%

Don’t Care

See

Table 2

See

Table 2

Key Specifications

Supply Voltages:........................................ V

DDQ3

= 3.3V±5%

DDQ2

= 2.5V±5%

CPU0:1 Output to Output Skew: ................................. 175 ps

Table 2. Spread Spectrum Feature

SPREAD#

Spread Profile

–0.5% (down spread)

0% (spread disabled)

Block Diagram

of the anchored frame as

<adjust the size

per requirement>

Pin Configuration

Rev 1.0, November 24, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

Page 1 of 8

www.SpectraLinear.com

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