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Spartan-3AN FPGA Family
Data Sheet
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DS557 November 19, 2009
Product Specification
Bitstream Sizes
Detailed Descriptions by Mode
·
Self-contained In-System Flash mode
·
Master Serial Mode using Platform Flash PROM
·
Master SPI Mode using Commodity Serial Flash
·
Master BPI Mode using Commodity Parallel Flash
·
Slave Parallel (SelectMAP) using a Processor
·
Slave Serial using a Processor
·
JTAG Mode
-
ISE iMPACT Programming Examples
-
MultiBoot Reconfiguration
-
Design Authentication using Device DNA
UG333:
Spartan-3AN In-System Flash User Guide
UG334:
Spartan-3AN Starter Kit User Guide
-
-
Module 1: Introduction and Ordering
Information
DS557-1 (v3.2) November 19, 2009
•
•
•
•
•
•
•
•
Introduction
Features
Architectural Overview
Configuration Overview
In-system Flash Memory Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
Module 2: Functional Description
DS557-2 (v3.2) November 19, 2009
The functionality of the Spartan®-3AN FPGA family is
described in the following documents:
•
UG331:
Spartan-3 Generation FPGA User Guide
-
Clocking Resources
-
Digital Clock Managers (DCMs)
-
Block RAM
-
Configurable Logic Blocks (CLBs)
·
Distributed RAM
·
SRL16 Shift Registers
·
Carry and Arithmetic Logic
-
I/O Resources
-
Embedded Multiplier Blocks
-
Programmable Interconnect
-
ISE® Design Tools and IP Cores
-
Embedded Processing and Control Solutions
-
Pin Types and Package Overview
-
Package Drawings
-
Powering FPGAs
-
Power Management
UG332:
Spartan-3 Generation Configuration User Guide
-
Configuration Overview
-
Configuration Pins and Behavior
•
•
Module 3: DC and Switching Characteristics
DS557-3 (v3.2) November 19, 2009
•
DC Electrical Characteristics
-
Absolute Maximum Ratings
-
Supply Voltage Specifications
-
Recommended Operating Conditions
Switching Characteristics
-
I/O Timing
-
Configurable Logic Block (CLB) Timing
-
Multiplier Timing
-
Block RAM Timing
-
Digital Clock Manager (DCM) Timing
-
Suspend Mode Timing
-
Device DNA Timing
-
Configuration and JTAG Timing
•
Module 4: Pinout Descriptions
DS557-4 (v3.2) November 19, 2009
•
•
•
•
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
•
Table 1:
Production Status of Spartan-3AN FPGAs
Spartan-3AN FPGA
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Status
Production
Production
Production
Production
Production
Additional information on the Spartan-3AN family can be found at
http://www.xilinx.com/products/spartan3a/3an.htm.
© Copyright 2007–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
DS557 November 19, 2009
Product Specification
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DS557 November 19, 2009
Product Specification
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Spartan-3AN FPGA Family:
Introduction and Ordering Information
Product Specification
DS557-1 (v3.2) November 19, 2009
Introduction
The Spartan®-3AN FPGA family combines the best
attributes of a leading edge, low cost FPGA with nonvolatile
technology across a broad range of densities. The family
combines all the features of the Spartan-3A FPGA family
plus leading technology in-system Flash memory for
configuration and nonvolatile data storage.
The Spartan-3AN FPGAs are part of the Extended
Spartan-3A family, which also includes the Spartan-3A
FPGAs and the higher density Spartan-3A DSP FPGAs.
The Spartan-3AN FPGA family is excellent for
space-constrained applications such as blade servers,
medical devices, automotive infotainment, telematics, GPS,
and other small consumer products. Combining FPGA and
Flash technology minimizes chip count, PCB traces and
overall size while increasing system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The
family maintains full support for external configuration. The
Spartan-3AN FPGA is the world’s first nonvolatile FPGA
with MultiBoot, supporting two or more configuration files in
one device, allowing alternative configurations for field
upgrades, test modes, or multiple system configurations.
•
•
•
Robust 100K Flash memory program/erase cycles
20 years Flash memory data retention
Security features provide bitstream anti-cloning protection
♦
Buried configuration interface
♦
Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
♦
Flash memory sector protection and lockdown
Configuration watchdog timer automatically recovers from
configuration errors
Suspend mode reduces system power consumption
♦
Retains all design state and FPGA configuration data
♦
Fast response time, typically less than 100
μs
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO™ interface pins
♦
Up to 502 I/O pins or 227 differential signal pairs
♦
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
♦
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
♦
Up to 24 mA output drive
♦
3.3V
±10%
compatibility and hot swap compliance
♦
622+ Mb/s data transfer rate per I/O
♦
DDR/DDR2 SDRAM support up to 400 Mb/s
♦
LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL
differential I/O
Abundant, flexible logic resources
♦
Densities up to 25,344 logic cells
♦
Optional shift register or distributed RAM support
♦
Enhanced 18 x 18 multipliers with optional pipeline
Hierarchical SelectRAM™ memory architecture
♦
Up to 576 Kbits of dedicated block RAM
♦
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
Complete Xilinx®
ISE®
and
WebPACK™
software
development system support
MicroBlaze™
and
PicoBlaze™
embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI™ technology support
Low-cost QFP and BGA Pb-free (RoHS) packaging options
♦
Pin-compatible with the same packages in the
Spartan-3A FPGA family
•
•
•
•
•
Features
•
•
The new standard for low cost nonvolatile FPGA solutions
Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
♦
Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
Integrated robust configuration memory
♦
Saves board space
♦
Improves ease-of-use
♦
Simplifies design
♦
Reduces support issues
Plentiful amounts of nonvolatile memory available to the user
♦
Up to 11+ Mb available
♦
MultiBoot support
♦
Embedded processing and code shadowing
♦
Scratchpad memory
Equivalent
Logic
Cells
1,584
4,032
8,064
13,248
25,344
•
•
•
•
•
•
•
•
•
Table 2:
Summary of Spartan-3AN FPGA Attributes
Device
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
System
Gates
50K
200K
400K
700K
1400K
CLBs
176
448
896
1472
2816
Distributed
Slices RAM Bits
(1)
704
11K
1792
28K
3,584
56K
5,888
92K
11,264
176K
Block
RAM
Bits
(1)
54K
288K
360K
360K
576K
Maximum
Dedicated
Maximum Differential Bitstream In-System
Multipliers DCMs User I/O
I/O Pairs
Size
(1)
Flash Bits
3
2
108
50
427K
1M
16
4
195
90
1,168K
4M
20
4
311
142
1,842K
4M
20
8
372
165
2,669K
8M
32
8
502
227
4,644K
16M
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
© Copyright 2007–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
DS557-1 (v3.2) November 19, 2009
Product Specification
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Introduction and Ordering Information
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Architectural Overview
The Spartan-3AN FPGA architecture is compatible with that
of the Spartan-3A FPGA. The architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. They support a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM
provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks
accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks
provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
•
•
These elements are organized as shown in
Figure 1.
A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50AN, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50AN has DCMs only at the
top, while the XC3S700AN and XC3S1400AN add two
DCMs in the middle of the two columns of block RAM and
multipliers.
The Spartan-3AN FPGA features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
X-Ref Target - Figure 1
IOBs
CLB
Block RAM
DCM
IOBs
OBs
DCM
CLBs
IOBs
DCM
Block RAM / Multiplier
IOBs
Notes:
1.
IOBs
Multiplier
DS557-1_01_122006
The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1:
Spartan-3AN Family Architecture
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DS557-1 (v3.2) November 19, 2009
Product Specification
R
Introduction and Ordering Information
X-Ref Target - Figure 2
Spartan-3AN
FPGA
Configure
from internal
Flash memory
‘0’
‘1’
‘1’
M2
M1
M0
VCCAUX
INIT_B
DONE
3.3V
Indicates when
configuration is
finished
DS557-1_06_013107
Figure 2:
Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory
Configuration
Spartan-3AN FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored on-chip in nonvolatile Flash
memory, or externally in a PROM or some other nonvolatile
medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven
different modes:
•
Configure from internal SPI Flash memory (Figure
2)
♦
♦
♦
In-System Flash Memory
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in
Table 3,
used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.
Table 3:
Spartan-3AN Device In-System Flash Memory
Part
Number
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
1.
Completely self-contained
Reduced board space
Easy-to-use configuration interface
Total Flash
Memory
(Bits)
1,081,344
4,325,376
4,325,376
8,650,752
17,301,504
FPGA
Bitstream
(Bits)
437,312
1,196,128
1,886,560
2,732,640
4,755,296
Additional
Flash
Memory
(Bits)
(1)
642,048
3,127,872
2,437,248
5,917,824
12,545,280
•
•
•
•
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an external
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester
Aligned to next available page location.
After configuration, the FPGA design has full access to the
in-system Flash memory via an internal SPI interface; the
control logic is implemented with FPGA logic. Additionally,
the FPGA application itself can store nonvolatile data or
provide live, in-system Flash updates.
The Spartan-3AN device in-system Flash memory supports
leading-edge serial Flash features.
•
•
•
•
Small page size (264 or 528 bytes) simplifies
nonvolatile data storage
Randomly accessible, byte addressable
Up to 66 MHz serial data transfers
SRAM page buffers
♦
♦
♦
The MultiBoot feature stores multiple configuration files in
the on-chip Flash, providing extended life with field
upgrades. MultiBoot also supports multiple system
solutions with a single board to minimize inventory and
simplify the addition of new features, even in the field.
Flexibility is maintained to do additional MultiBoot
configurations via the external configuration method.
The Spartan-3AN device authentication protocol prevents
cloning. Design cloning, unauthorized overbuilding, and
complete reverse engineering have driven device security
requirements to higher and higher levels. Authentication
moves the security from bitstream protection to the next
generation of design-level security protecting both the
design and embedded microcode. The authentication
algorithm is entirely user defined, implemented using FPGA
logic. Every product, generation, or design can have a
different algorithm and functionality to enhance security.
DS557-1 (v3.2) November 19, 2009
Product Specification
Read Flash data while programming another Flash
page
EEPROM-like byte write functionality
Two buffers in most devices, one in XC3S50AN
•
•
Page, Block, and Sector Erase
Sector-based data protection and security features
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