MT41J512M14DA-187:H datasheet, PDF

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MT41J512M14DA-187:H: DescriptionDDR DRAM, 512MX4, CMOS, PBGA78, 8 X 10.50 MM, LEAD FREE, FBGA-78; Categorystorage storage; File Size12MB，210 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41J512M14DA-187:H Overview

DDR DRAM, 512MX4, CMOS, PBGA78, 8 X 10.50 MM, LEAD FREE, FBGA-78

MT41J512M14DA-187:H Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	78
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78
JESD-609 code	e1
length	10.5 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	78
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
organize	512MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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2Gb: x4, x8, x16 DDR3 SDRAM

Features

DDR3 SDRAM

MT41J512M4 – 64 Meg x 4 x 8 Banks

MT41J256M8 – 32 Meg x 8 x 8 Banks

MT41J128M16 – 16 Meg x 16 x 8 Banks

Features

•

= V

DDQ

= +1.5V ±0.075V

1.5V center-terminated push/pull I/O

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

CAS READ latency (CL): 5, 6, 7, 8, 9, 10, or 11

POSTED CAS ADDITIVE latency (AL): 0, CL - 1,

CL - 2

CAS WRITE latency (CWL): 5, 6, 7, 8, based on

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

of 0°C to +95°C

–

64ms, 8192 cycle refresh at 0°C to +85°C

–

32ms, 8192 cycle refresh at +85°C to +95°C

Clock frequency range of 300–800 MHz

Self refresh temperature (SRT)

Write leveling

Multipurpose register

Output driver calibration

Options

•

Configuration

–

512 Meg x 4

–

256 Meg x 8

–

128 Meg x 16

•

FBGA package (Pb-free) – x4, x8

–

78-ball (8mm x 10.5mm) Rev. H

–

78-ball (9mm x 11.5mm) Rev. D

–

82-ball (12.5mm x 15mm) Rev. A

•

FBGA package (Pb-free) – x16

–

96-ball (9mm x 14mm) Rev. D

•

Timing – cycle time

–

1.07ns @ CL = 13 (DDR3-1866)

–

1.25ns @ CL = 11 (DDR3-1600)

–

1.5ns @ CL = 10 (DDR3-1333)

–

1.5ns @ CL = 9 (DDR3-1333)

–

1.87ns @ CL = 8 (DDR3-1066)

–

1.87ns @ CL = 7 (DDR3-1066)

•

Operating temperature

–

Commercial (0°C

≤

+95°C)

–

Industrial (–40°C

≤

+95°C)

•

Revision

Note:

Marking

512M4

256M8

128M16

-107

-125

-15

-15E

-187

-187E

None

:A/:D/:H

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on

http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2

-125

1, 2

-15

-15E

-187

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

10-10-10

9-9-9

8-8-8

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1066, CL = 8 (-187).

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x4, x8, x16 DDR3 SDRAM

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature .............................................................................................................................. 12

General Notes ............................................................................................................................................ 12

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ...................................................................................................................................... 25

Electrical Specifications .................................................................................................................................. 29

Absolute Ratings ........................................................................................................................................ 29

Input/Output Capacitance ......................................................................................................................... 30

Thermal Characteristics .................................................................................................................................. 31

Electrical Specifications – I

Specifications and Conditions Definitions .......................................................... 32

Electrical Characteristics – I

Specifications .................................................................................................. 43

Electrical Specifications – DC and AC .............................................................................................................. 48

DC Operating Conditions ........................................................................................................................... 48

Input Operating Conditions ........................................................................................................................ 48

AC Overshoot/Undershoot Specification ..................................................................................................... 51

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 54

Slew Rate Definitions for Differential Input Signals ...................................................................................... 56

ODT Characteristics ....................................................................................................................................... 57

ODT Resistors ............................................................................................................................................ 57

ODT Sensitivity .......................................................................................................................................... 59

ODT Timing Definitions ............................................................................................................................. 59

Output Driver Impedance ............................................................................................................................... 63

34 Ohm Output Driver Impedance .............................................................................................................. 64

34 Ohm Driver ............................................................................................................................................ 65

34 Ohm Output Driver Sensitivity ................................................................................................................ 66

Alternative 40 Ohm Driver .......................................................................................................................... 67

40 Ohm Output Driver Sensitivity ................................................................................................................ 67

Output Characteristics and Operating Conditions ........................................................................................... 69

Reference Output Load ............................................................................................................................... 71

Slew Rate Definitions for Single-Ended Output Signals ................................................................................ 72

Slew Rate Definitions for Differential Output Signals ................................................................................... 73

Speed Bin Tables ............................................................................................................................................ 74

Electrical Characteristics and AC Operating Conditions ................................................................................... 78

Command and Address Setup, Hold, and Derating .......................................................................................... 97

Data Setup, Hold, and Derating ..................................................................................................................... 105

Commands – Truth Tables ............................................................................................................................. 112

Commands ................................................................................................................................................... 115

DESELECT ................................................................................................................................................ 115

NO OPERATION ........................................................................................................................................ 115

ZQ CALIBRATION LONG ........................................................................................................................... 115

ZQ CALIBRATION SHORT ......................................................................................................................... 115

ACTIVATE ................................................................................................................................................. 115

READ ........................................................................................................................................................ 115

WRITE ...................................................................................................................................................... 116

PRECHARGE ............................................................................................................................................. 116

REFRESH .................................................................................................................................................. 117

SELF REFRESH .......................................................................................................................................... 118

DLL Disable Mode ..................................................................................................................................... 119

Contents

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x4, x8, x16 DDR3 SDRAM

Input Clock Frequency Change ...................................................................................................................... 123

Write Leveling ............................................................................................................................................... 125

Write Leveling Procedure ........................................................................................................................... 127

Write Leveling Mode Exit Procedure ........................................................................................................... 129

Initialization ................................................................................................................................................. 130

Mode Registers .............................................................................................................................................. 132

Mode Register 0 (MR0) .................................................................................................................................. 133

Burst Length ............................................................................................................................................. 133

Burst Type ................................................................................................................................................ 134

DLL RESET ................................................................................................................................................ 135

Write Recovery .......................................................................................................................................... 135

Precharge Power-Down (Precharge PD) ..................................................................................................... 136

CAS Latency (CL) ....................................................................................................................................... 136

Mode Register 1 (MR1) .................................................................................................................................. 137

DLL Enable/DLL Disable ........................................................................................................................... 137

Output Drive Strength ............................................................................................................................... 138

OUTPUT ENABLE/DISABLE ...................................................................................................................... 138

TDQS Enable ............................................................................................................................................. 138

On-Die Termination .................................................................................................................................. 139

WRITE LEVELING ..................................................................................................................................... 139

POSTED CAS ADDITIVE Latency ................................................................................................................ 139

Mode Register 2 (MR2) .................................................................................................................................. 141

CAS Write Latency (CWL) ........................................................................................................................... 141

AUTO SELF REFRESH (ASR) ...................................................................................................................... 142

SELF REFRESH TEMPERATURE (SRT) ....................................................................................................... 142

SRT vs. ASR ............................................................................................................................................... 143

DYNAMIC ODT ......................................................................................................................................... 143

Mode Register 3 (MR3) .................................................................................................................................. 144

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144

MPR Functional Description ...................................................................................................................... 145

MPR Register Address Definitions and Bursting Order ................................................................................ 146

MPR Read Predefined Pattern .................................................................................................................... 151

MODE REGISTER SET (MRS) Command ........................................................................................................ 151

ZQ CALIBRATION Operation ......................................................................................................................... 152

ACTIVATE Operation ..................................................................................................................................... 153

READ Operation ............................................................................................................................................ 155

WRITE Operation .......................................................................................................................................... 166

DQ Input Timing ....................................................................................................................................... 174

PRECHARGE Operation ................................................................................................................................. 176

SELF REFRESH Operation ............................................................................................................................. 176

Extended Temperature Usage ........................................................................................................................ 178

Power-Down Mode ....................................................................................................................................... 179

RESET Operation ........................................................................................................................................... 187

On-Die Termination (ODT) ........................................................................................................................... 189

Functional Representation of ODT ............................................................................................................. 189

Nominal ODT ........................................................................................................................................... 189

Dynamic ODT ............................................................................................................................................... 191

Functional Description .............................................................................................................................. 191

Synchronous ODT Mode ............................................................................................................................... 196

ODT Latency and Posted ODT ................................................................................................................... 196

Timing Parameters .................................................................................................................................... 196

ODT Off During READs .............................................................................................................................. 199

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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