FSGS033R
Data Sheet
December 2001
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFET
Fairchild Star*Power Rad Hard
MOSFETs have been specifically
TM
developed for high performance
applications in a commercial or
military space environment.
Star*Power MOSFETs offer the system designer both
extremely low r
DS(ON)
and Gate Charge allowing the
development of low loss Power Subsystems. Star*Power
Gold FETs combine this electrical capability with total dose
radiation hardness up to 100 krads while maintaining the
guaranteed performance for Single Event Effects (SEE)
which the Fairchild FS families have always featured.
The Fairchild family of Star*Power FETs includes a series of
devices in various voltage, current and package styles. The
portfolio consists of Star*Power and Star*Power Gold
products. Star*Power FETs are optimized for total dose and
r
DS(ON)
while exhibiting SEE capability at full rated voltage
up to an LET of 37. Star*Power Gold FETs have been
optimized for SEE and Gate Charge combining SEE
performance to 80% of the rated voltage for an LET of 82
with extremely low gate charge characteristics.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is specifically designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, power
distribution, motor drives and relay drivers as well as other
power control and conditioning applications. As with
conventional MOSFETs these Radiation Hardened
MOSFETs offer ease of voltage control, fast switching
speeds and ability to parallel switching devices.
Reliability screening is available as either TXV or Space
equivalent of MIL-PRF-19500.
Formerly available as type TA45222W.
Features
• 16A (Current Limited by Package), 30V, r
DS(ON)
= 0.020Ω
• UIS Rated
• Total Dose
- Meets Pre-RAD Specifications to 100 krad (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 82MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
AS
• Photo Current
- 1.0nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cm
2
Symbol
D
G
S
Packaging
TO-257AA
S
D
G
Ordering Information
RAD LEVEL
10K
100K
100K
SCREENING LEVEL
PART NUMBER/BRAND
CAUTION: Beryllia Warning per MIL-PRF-19500
refer to package specifications.
Engineering Samples FSGS033D1
TXV
Space
FSGS033R3
FSGS033R4
©2001 Fairchild Semiconductor Corporation
FSGS033R Rev. B
FSGS033R
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSGS033R
30
30
16 (Note)
16 (Note)
64
±24
57
23
0.45
64
16
64
-55 to 150
300
4.4 (Typical)
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: Current limited by package.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
30
-
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 12V
V
DD
= 15V,
I
D
= 16A
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 2V
I
D
= 16A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.018
-
-
-
-
-
35
11
8
60
4
5.5
1850
1120
35
-
MAX
-
5.5
4.5
-
25
250
100
200
0.320
0.020
0.030
20
65
30
15
38
14
10
-
-
-
-
-
-
2.2
UNITS
V
V
V
V
µA
µA
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(12)
Q
gs
Q
gd
Q
g(20)
Q
g(TH)
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= 24V,
V
GS
= 0V
V
GS
=
±24V
V
GS
= 12V, I
D
= 16A
I
D
= 16A,
V
GS
= 12V
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge Source
Gate Charge Drain
Gate Charge at 20V
Threshold Gate Charge
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
V
DD
= 15V, I
D
= 16A,
R
L
= 0.94Ω, V
GS
= 12V,
R
GS
= 7.5Ω
©2001 Fairchild Semiconductor Corporation
FSGS033R Rev. B
FSGS033R
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
SYMBOL
V
SD
t
rr
Q
RR
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±24V,
V
DS
= 0V
V
GS
= 0, V
DS
= 24V
V
GS
= 12V, I
D
= 16A
V
GS
= 12V, I
D
= 16A
MIN
30
2.0
-
-
-
-
MAX
-
4.5
100
25
0.320
0.020
UNITS
V
V
nA
µA
V
Ω
I
SD
= 16A
I
SD
= 16A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
90
MAX
1.2
70
-
UNITS
V
ns
nC
Electrical Specifications up to 100 krad
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
(NOTE 6)
TYPICAL LET
(MeV/mg/cm)
37
60
60
82
82
NOTES:
4. Testing conducted at Brookhaven National Labs or Texas A&M.
5. Fluence = 1E5 ions/cm
2
(Typ), T = 25
o
C.
6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au.
7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
APPLIED
V
GS
BIAS
(V)
-5
-2
-5
0
-2
(NOTE 7)
MAXIMUM
V
DS
BIAS
(V)
30
30
22.5
24
22.5
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
TYPICAL RANGE (µ)
36
32
32
28
28
Performance Curves
Unless Otherwise Specified
40
LET = 37
30
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LET = 60MeV/mg/cm
2
, RANGE = 32µ
LET = 82MeV/mg/cm
2
, RANGE = 28µ
40
TEMP = 25
o
C
30
V
DS
(V)
V
DS
(V)
20
20
10
10
LET = 82
LET = 60
0
0
-1
-2
-3
-4
V
GS
(V)
-5
-6
-7
0
0
4
8
12
V
GS
(V)
16
20
24
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. TYPICAL SEE SIGNATURE CURVE
©2001 Fairchild Semiconductor Corporation
FSGS033R Rev. B
FSGS033R
Performance Curves
1E-3
LIMITING INDUCTANCE (HENRY)
20
1E-4
Unless Otherwise Specified
(Continued)
30A
1E-5
100A
300A
1E-6
I
D
, DRAIN (A)
ILM = 10A
16
12
8
4
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
0
-50
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO
LIMIT GAMMA DOT CURRENT TO I
AS
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
300
T
C
= 25
o
C
100
I
D
, DRAIN CURRENT (A)
100µs
12V
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
0.1
1
10
100
CHARGE
V
G
Q
GS
Q
GD
Q
G
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. BASIC GATE CHARGE WAVEFORM
2.5
I
D
, DRAIN TO SOURCE CURRENT (A)
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 16A
2.0
NORMALIZED r
DS(ON)
50
40
V
GS
= 6V
30
1.5
1.0
20
0.5
10
V
GS
= 4V
0
0
1
2
3
4
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 7. TYPICAL NORMALIZED r
DS(ON)
vs JUNCTION
TEMPERATURE
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
FSGS033R Rev. B
FSGS033R
Performance Curves
NORMALIZED THERMAL RESPONSE (Z
qJC
)
10
1
Unless Otherwise Specified
(Continued)
10
0
0.5
10
-1
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
P
DM
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
+ T
C
10
-4
10
-3
10
-2
10
-1
10
0
t
1
10
-2
t
2
10
1
10
-3 -5
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
I
AS
, AVALANCHE CURRENT (A)
100
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
10
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
1
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
10
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSGS033R Rev. B
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