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FSGJ164R3

Description
Power Field-Effect Transistor, 65A I(D), 150V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA
CategoryDiscrete semiconductor    The transistor   
File Size107KB，7 Pages
ManufacturerInternational Rectifier （ Infineon ）
Websitehttp://www.irf.com/
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FSGJ164R3 Overview

Power Field-Effect Transistor, 65A I(D), 150V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA

FSGJ164R3 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerInternational Rectifier （ Infineon ）
package instructionFLANGE MOUNT, S-PSFM-P3
Reach Compliance Codecompliant
ECCN codeEAR99
Shell connectionISOLATED
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage150 V
Maximum drain current (ID)65 A
Maximum drain-source on-resistance0.024 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-254AA
JESD-30 codeS-PSFM-P3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeSQUARE
Package formFLANGE MOUNT
Peak Reflow Temperature (Celsius)235
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)200 A
Certification statusNot Qualified
surface mountNO
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal locationSINGLE
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON

FSGJ164R3 Preview

FSGJ164R
Data Sheet
December 2001
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFET
Fairchild Star*Power Rad Hard
MOSFETs have been specifically
TM
developed for high performance
applications in a commercial or
military space environment.
Star*Power MOSFETs offer the system designer both
extremely low r
DS(ON)
and Gate Charge allowing the
development of low loss Power Subsystems. Star*Power
Gold FETs combine this electrical capability with total dose
radiation hardness up to 100 krads while maintaining the
guaranteed performance for Single Event Effects (SEE)
which the Fairchild FS families have always featured.
The Fairchild family of Star*Power FETs includes a series of
devices in various voltage, current and package styles. The
portfolio consists of Star*Power and Star*Power Gold
products. Star*Power FETs are optimized for total dose and
r
DS(ON)
while exhibiting SEE capability at full rated voltage
up to an LET of 37. Star*Power Gold FETs have been
optimized for SEE and Gate Charge combining SEE
performance to 80% of the rated voltage for an LET of 82
with extremely low gate charge characteristics.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is specifically designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, power
distribution, motor drives and relay drivers as well as other
power control and conditioning applications. As with
conventional MOSFETs these Radiation Hardened
MOSFETs offer ease of voltage control, fast switching
speeds and ability to parallel switching devices.
Reliability screening is available as either TXV or Space
equivalent of MIL-PRF-19500.
Formerly available as type TA45229W.
Features
• 65A, 150V, r
DS(ON)
= 0.024Ω
• UIS Rated
• Total Dose
- Meets Pre-rad Specifications to 100 krad (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 82MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 5V Off-Bias
• Dose Rate
- Typically Survives 3E9 rad (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
AS
• Photo Current
- 14nA Per-rad (Si)/s Typically
• Neutron
- Maintain Pre-rad Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Symbol
D
G
S
Packaging
TO-254AA
G
S
D
Ordering Information
RAD LEVEL
10K
100K
100K
SCREENING LEVEL
PART NUMBER/BRAND
Engineering Samples FSGJ164D1
TXV
Space
FSGJ164R3
FSGJ164R4
CAUTION: Beryllia Warning per MIL-PRF-19500
refer to package specifications.
©2001 Fairchild Semiconductor Corporation
FSGJ164R Rev. B
FSGJ164R
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSGJ164R
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical)
192
77
1.54
130
65
200
-55 to 150
300
9.3 (Typical)
W
W
W/
o
C
A
A
A
o
C
o
C
UNITS
V
V
A
A
A
V
150
150
65
41
200
±30
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
150
-
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 12V
V
DD
= 75V,
I
D
= 65A
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 2V
I
D
= 65A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.018
-
-
-
-
-
100
35
35
160
12
7.5
5700
1160
45
-
MAX
-
5.5
4.5
-
25
250
100
200
1.690
0.024
0.044
35
160
65
15
115
45
45
-
-
-
-
-
-
0.65
UNITS
V
V
V
V
µA
µA
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 120V,
V
GS
= 0V
V
GS
=
±30V
Gate to Source Leakage Current
I
GSS
Drain to Source On-State Voltage
Drain to Source On Resistance
V
DS(ON)
r
DS(ON)12
V
GS
= 12V, I
D
= 65A
I
D
= 41A,
V
GS
= 12V
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge Source
Gate Charge Drain
Gate Charge at 20V
Threshold Gate Charge
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(12)
Q
gs
Q
gd
Q
g(20)
Q
g(TH)
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DD
= 75V, I
D
= 65A,
R
L
= 1.14Ω, V
GS
= 12V,
R
GS
= 2.35Ω
©2001 Fairchild Semiconductor Corporation
FSGJ164R Rev. B
FSGJ164R
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
SYMBOL
V
SD
t
rr
Q
RR
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±30V,
V
DS
= 0V
V
GS
= 0, V
DS
= 120V
V
GS
= 12V, I
D
= 65A
V
GS
= 12V, I
D
= 41A
MIN
150
2.0
-
-
-
-
MAX
-
4.5
100
25
1.690
0.024
UNITS
V
V
nA
µA
V
Ω
I
SD
= 65A
I
SD
= 65A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
3.2
MAX
1.2
370
-
UNITS
V
ns
µC
Electrical Specifications up to 100 krad
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
(NOTE 6)
TYPICAL LET
(MeV/mg/cm)
37
60
82
82
NOTES:
4. Testing conducted at Brookhaven National Labs or Texas A&M.
5. Fluence = 1E5 ions/cm
2
(Typ), T = 25
o
C.
6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au.
7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
APPLIED
V
GS
BIAS
(V)
-20
-10
-5
-10
(NOTE 7)
MAXIMUM
V
DS
BIAS
(V)
150
150
120
90
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
TYPICAL RANGE (µ)
36
32
28
28
Performance Curves
Unless Otherwise Specified
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LET = 60MeV/mg/cm
2
, RANGE = 32µ
LET = 82MeV/mg/cm
2
, RANGE = 28µ
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
150
200
LET = 37
160
V
DS
(V)
100
V
DS
(V)
120
80
LET = 82
50
40
TEMP = 25
o
C
LET = 60
0
-8
-12
V
GS
(V)
-16
-20
-24
0
5
10
15
20
25
30
35
40
NEGATIVE V
GS
BIAS (V)
0
0
-4
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. TYPICAL SEE SIGNATURE CURV E
©2001 Fairchild Semiconductor Corporation
FSGJ164R Rev. B
FSGJ164R
Performance Curves
1E-3
LIMITING INDUCTANCE (HENRY)
Unless Otherwise Specified
(Continued)
80
70
1E-4
ILM = 10A
I
D
, DRAIN (A)
30A
1E-5
100A
300A
1E-6
60
50
40
30
20
10
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
0
-50
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO
LIMIT GAMMA DOT CURRENT TO I
AS
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
500
25
0
C
I
D
, DRAIN CURRENT (A)
100
12V
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
500
V
G
10ms
Q
GS
Q
G
Q
GD
CHARGE
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. BASIC GATE CHARGE WAVEFORM
2.5
I
D
, DRAIN TO SOURCE CURRENT (A)
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 41A
NORMALIZED r
DS(ON)
2.0
200
V
GS
= 14V
V
GS
= 12V
160 V
GS
= 10V
V
GS
= 8V
V
GS
= 6V
120
1.5
1.0
80
V
GS
= 6V
40
0.5
0.0
-80
0
0
2
4
6
8
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 7. TYPICAL NORMALIZED r
DS(ON)
vs JUNCTION
TEMPERATURE
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
FSGJ164R Rev. B
FSGJ164R
Performance Curves
10
NORMALIZED THERMAL RESPONSE (Z
θJC
)
Unless Otherwise Specified
(Continued)
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
10
-4
10
-3
10
-2
10
-1
10
0
P
DM
t
1
0.01
t
2
10
1
0.001
10
-5
t, RECTANGULAR PULSE DURATION (s)
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
1000
I
AS
, AVALANCHE CURRENT (A)
100
STARTING T
J
= 150
o
C
10
STARTING T
J
= 25
o
C
1
0.01
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSGJ164R Rev. B
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FSGJ164R3 Related Products

FSGJ164R3 FSGJ164R4 FSGJ164D1
Description Power Field-Effect Transistor, 65A I(D), 150V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA Power Field-Effect Transistor, 65A I(D), 150V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA Power Field-Effect Transistor, 65A I(D), 150V, 0.024ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA
Is it lead-free? Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible
Maker International Rectifier （ Infineon ） International Rectifier （ Infineon ） International Rectifier （ Infineon ）
package instruction FLANGE MOUNT, S-PSFM-P3 FLANGE MOUNT, S-PSFM-P3 FLANGE MOUNT, S-PSFM-P3
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
Shell connection ISOLATED ISOLATED ISOLATED
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 150 V 150 V 150 V
Maximum drain current (ID) 65 A 65 A 65 A
Maximum drain-source on-resistance 0.024 Ω 0.024 Ω 0.024 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code TO-254AA TO-254AA TO-254AA
JESD-30 code S-PSFM-P3 S-PSFM-P3 S-PSFM-P3
JESD-609 code e0 e0 e0
Number of components 1 1 1
Number of terminals 3 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape SQUARE SQUARE SQUARE
Package form FLANGE MOUNT FLANGE MOUNT FLANGE MOUNT
Peak Reflow Temperature (Celsius) 235 235 235
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL
Maximum pulsed drain current (IDM) 200 A 200 A 200 A
Certification status Not Qualified Not Qualified Not Qualified
surface mount NO NO NO
Terminal surface TIN LEAD TIN LEAD TIN LEAD
Terminal form PIN/PEG PIN/PEG PIN/PEG
Terminal location SINGLE SINGLE SINGLE
Maximum time at peak reflow temperature 30 30 30
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON

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