SI4330-B1-FMR datasheet, PDF - EEWORLD Datasheet

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SI4330-B1-FMR: DescriptionSPECIALTY TELECOM CIRCUIT, QCC20; CategoryTopical application Wireless rf/communication; File Size532KB，64 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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SI4330-B1-FMR Overview

SPECIALTY TELECOM CIRCUIT, QCC20

SI4330-B1-FMR Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	3 V
Processing package description	铅 FREE, MO-220VGGD-8, QFN-20
state	ACTIVE
packaging shape	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes
Terminal form	NO
Terminal spacing	0.5000 mm
Terminal location	Four
Packaging Materials	UNSPECIFIED
Temperature level	INDUSTRIAL
Communication type	telecommunications circuits

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Si4330-B1

Si4330 ISM R

ECEIVER

Features



Frequency Range = 240–960 MHz

Sensitivity = –121 dBm

Low Power Consumption



18.5 mA receive

Data Rate = 0.123 to 256 kbps

FSK, GFSK, and OOK modulation

Power Supply = 1.8 to 3.6 V

Ultra low power shutdown mode

Digital RSSI

Wake-up timer

Auto-frequency calibration (AFC)

Clear channel assessment

Programmable RX BW 2.6–620 kHz

Programmable packet handler



Programmable GPIOs

Embedded antenna diversity

algorithm

Configurable packet handler

Preamble detector

RX 64 byte FIFO

Low battery detector

Temperature sensor and 8-bit ADC

–40 to +85 °C temperature range

Integrated voltage regulators

Frequency hopping capability

On-chip crystal tuning

20-Pin QFN package

Low BOM

Power-on-reset (POR)

Ordering Information:

See page 63.

Pin Assignments

Si4330

XOUT

nSEL

15 SCLK

14 SDI

13 SDO

12 VDD_DIG

GPIO_0

GPIO_1

GPIO_2

10 11 NC

VR_DIG

nIRQ

SDN

Applications



Remote control

Home security & alarm

Telemetry

Personal data logging

Toy control

Tire pressure monitoring

Wireless PC peripherals



Remote meter reading

Remote keyless entry

Home automation

Industrial control

Sensor networks

Health monitors

Tag readers

VDD_RF 1

NC 2

RXp 3

RXn 4

NC 5

ANT1

20 19 18 17 16

Description

Silicon Laboratories’ Si4330 is a highly integrated, single chip wireless ISM

receiver. The high-performance EZRadioPRO

family includes a complete line of

transmitters, receivers, and transceivers allowing the RF system designer to

choose the optimal wireless part for their application.

The Si4330 offers advanced radio features including continuous frequency

coverage from 240–960 MHz. The Si4330’s high level of integration offers

reduced BOM cost while simplifying the overall system design. The extremely low

receive sensitivity (–121 dBm) ensures extended range and improved link

performance. Built-in antenna diversity and support for frequency hopping can be

used to further extend range and enhance performance.

Additional system features such as an automatic wake-up timer, low battery

detector, 64 byte RX FIFO, automatic packet handling, and preamble detection

reduce overall current consumption and allow the use of a lower-cost system

MCU. An integrated temperature sensor, general purpose ADC, power-on-reset

(POR), and GPIOs further reduce overall system cost and size.

The Si4330’s digital receive architecture features a high-performance ADC and

DSP based modem which performs demodulation, filtering, and packet handling

for increased flexibility and performance.

An easy-to-use calculator is provided to quickly configure the radio settings,

simplifying customer's system design and reducing time to market.

Patents pending

Rev 1.0 12/09

XIN

GND

PAD

Si4330

Si4330-B1

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.3. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.8. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.9. Receive Header Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Rev 1.0

Si4330-B1

8.6. Wake-Up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.9. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

10. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

15. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

15.1. Si4330 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

15.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16. Package Outline: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17. PCB Land Pattern: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Rev 1.0

Si4330-B1

I S T OF

IGURES

Figure 1. RX Application Example............................................................................................ 14

Figure 2. SPI Timing.................................................................................................................. 16

Figure 3. SPI Timing—READ Mode ..........................................................................................17

Figure 4. SPI Timing—Burst Write Mode .................................................................................. 17

Figure 5. SPI Timing—Burst Read Mode .................................................................................. 17

Figure 6. State Machine Diagram.............................................................................................. 18

Figure 7. RX Timing .................................................................................................................. 22

Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset .................................................. 26

Figure 9. PLL Synthesizer Block Diagram................................................................................. 30

Figure 10. FIFO Threshold ........................................................................................................32

Figure 11. Packet Structure....................................................................................................... 33

Figure 12. Required RX Packet Structure with Packet Handler Disabled ................................. 33

Figure 13. Multiple Packets in RX Packet Handler.................................................................... 34

Figure 14. Multiple Packets in RX with CRC or Header Error ................................................... 34

Figure 15. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 36

Figure 16. Manchester Coding Example ...................................................................................36

Figure 17. Header ..................................................................................................................... 38

Figure 18. POR Glitch Parameters............................................................................................ 40

Figure 19. General Purpose ADC Architecture ......................................................................... 42

Figure 20. Temperature Ranges using ADC8 ........................................................................... 44

Figure 21. WUT Interrupt and WUT Operation.......................................................................... 47

Figure 22. Low Duty Cycle Mode .............................................................................................. 48

Figure 23. RSSI Value vs. Input Power..................................................................................... 51

Figure 24. Receiver—Schematic Receiver—Top...................................................................... 52

Figure 25. 20-Pin Quad Flat No-Lead (QFN) ............................................................................60

Figure 26. PCB Land Pattern .................................................................................................... 61

Rev 1.0

SI4330-B1-FMR Related Products

	SI4330-B1-FMR	SI4330-B1
Description	SPECIALTY TELECOM CIRCUIT, QCC20	SPECIALTY TELECOM CIRCUIT, QCC20
Number of functions	1	1
Number of terminals	20	20
Maximum operating temperature	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Rated supply voltage	3 V	3 V
Processing package description	铅 FREE, MO-220VGGD-8, QFN-20	铅 FREE, MO-220VGGD-8, QFN-20
state	ACTIVE	ACTIVE
packaging shape	SQUARE	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes	Yes
Terminal form	NO	NO
Terminal spacing	0.5000 mm	0.5000 mm
Terminal location	Four	Four
Packaging Materials	UNSPECIFIED	UNSPECIFIED
Temperature level	INDUSTRIAL	INDUSTRIAL
Communication type	telecommunications circuits	telecommunications circuits

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