Si5315-EVB datasheet, PDF - EEWORLD Datasheet

Si5315-EVB: DescriptionSYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER; File Size414KB，54 Pages; ManufacturerSILABS; Websitehttp://www.silabs.com

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Si5315-EVB Overview

SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

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Si5315

Y N C H R O N O U S

T H E R N E T

/ T

E L E C O M

I T T E R

T T E N U A T I N G

LOCK

ULTIPLIER

Features



Provides jitter attenuation and frequency



translation between SONET/PDH and

Ethernet



Supports ITU-T G.8262 Synchronous

Ethernet equipment slave clock (EEC

option 1 and 2) requirements with



optional Stratum 3 compliant timing card

clock source

Two clock inputs/two clock outputs



Input frequency range: 8 kHz–644 MHz



Output frequency range: 8 kHz–644 MHz



Ultra low jitter:

0.23 ps RMS (1.875–20 MHz)



0.47 ps RMS (12 kHz–20 MHz)



Simple pin control interface



Selectable loop bandwidth for jitter

attenuation: 60 to 8.4 kHz

Automatic/Manual hitless switching

and holdover during loss of inputs

clock

Programmable output clock signal

format: LVPECL, LVDS, CML or

CMOS

40 MHz crystal or XO reference

Single supply: 1.8, 2.5, or 3.3 V

On-chip voltage regulator with high

PSRR

Loss of lock and loss of signal alarms

Small size: 6 x 6 mm, 36-QFN

Wide temperature range: –40 to

+85 ºC

Ordering Information:

See page 48.

Applications



CKOUT1–

CKIN1–

CKOUT2+

CKOUT2–

Description

RST 1

36 35 34 33 32 31 30 29 28

27 FRQSEL3

26 FRQSEL2

25 FRQSEL1

The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous

Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE

EEC options 1 and 2 when paired with a timing card that implements the required

wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz

and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to

644.53 MHz. The input clock frequency and clock multiplication ratio are selectable

from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon

Laboratories' third-generation DSPLL

technology, which provides any-frequency

synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the

need for external VCXO and loop filter components. The DSPLL loop bandwidth is

user programmable, providing jitter performance optimization at the application level.

FRQTBL 2

LOS1 3

LOS2 4

VDD 5

XA 6

GND

CKOUT1+

24 FRQSEL0

23 BWSEL1

22 BWSEL0

21 CS_CA

20 GND

19 GND

LOL

SFOUT0

GND

Pad

GND 8

AUTOSEL 9

10 11 12 13 14 15 16 17 18

CKIN2+

XTAL/CLOCK

DBL2_BY

CKIN1+

CKIN2–

GND

VDD

Functional Block Diagram

XTAL/Clock

Si5315

Clock Out 1

Clock In 1

DSPLL

Clock In 2

Clock Out 2

Output Signal Format[1:0]

Loss of Lock

Loss of Signal 1

Loss of Signal 2

Clock 2 Disable/PLL Bypass

Status/Control

VDD (1.8, 2.5, or 3.3 V)

GND

Frequency Select[3:0]

Frequency Table Select

Loop Bandwidth Select[1:0]

Manual/Auto Clock Selection

Clock Switch/Clock Active Indicator

XTAL/Clock

Rev. 1.0 4/12

SFOUT1

Synchronous Ethernet line cards

SONET OC-3/12/48 line cards

PON OLT/ONU



Carrier Ethernet switches routers

MSAN / DSLAM

T1/E1/DS3/E3 line cards

Pin Assignments

VDD

Si5315

Si5315

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . .11

1.2. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . . 12

2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. System Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.1. Frequency Multiplication Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3. Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

7. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

7.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

8. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

9.1. 10G LAN SyncE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10. Pin Descriptions: Si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

13. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

14.1. Si5315 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Rev. 1.0

Si5315-EVB Related Products

	Si5315-EVB	Si5315A-C-GM
Description	SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER	SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

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