Integrated Linear DDR
Termination Regulator
POWER MANAGEMENT
Description
The SC2595 is an integrated linear DDR termination
device which provides a complete solution for DDR
termination designs while meeting the JEDEC require-
ments of SSTL-2 specifications for DDR-SDRAM
termination.
The SC2595 can source and sink 1.5A current at the
output V
TT
while maintaining excellent load regulation.
V
TT
is designed to track the V
REF
voltage with a tight
tolerance over the entire current range while preventing
shoot through on the output stage.
A V
SENSE
pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage.
The SC2595 incorporates a disable function built into
the AV
CC
pin to tri-state the output during Suspend To
Ram (STR) states.
(Multiple patents pending.)
SC2595
Features
Available in the SOIC-8L EDP or MLPQ-16 package
Regulates while sourcing or sinking 1.5A
AV
CC
range is from 2.5V to 5V
Reference output
Minimum number of external components
Accurate internal voltage divider
Disable function
Applications
DDR memory termination
High speed data line termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
Typical Application Circuit
VDD
2.5V
SC2595
1
2
3
VREF
1.25V
4
NC
GND
VSENSE
VREF
VTT
PVCC
AVCC
VDDQ
8
7
6
5
Cin1
Cin2
1uF
68uF
Cout1
220uF
Cout2
10uF
VTT
1.25V
Csense Cref
2.2uF
10nF
Revision: August. 08, 2005
1
www.semtech.com
SC2595
POWER MANAGEMENT
Absolute Maximum Ratings
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
P ar am et er
PVCC, AVCC, VDDQ to GN D
Thermal Resistance Junction to Case
SOIC-8L EDP
MLPQ-16
Thermal Resistance Junction to Ambient
SOIC-8L EDP
MLPQ-16
Op erating Temp erature Range
Op erating Junction Temp erature Range
Storage Temp erature Range
Peak IR Reflow Temp erature 10 - 40s
ESD Rating (Human Body Model)
S y m b ol
V
CC
θ
JC
M ax i m u m
-0.3 to +6.0
5.5
1.5
36.5
47
-40 to +105
-40 to +150
-65 to +150
260
2
Units
V
°C/W
θ
JA
T
A
T
J
T
STG
T
LE A D
ESD
°C/W
°C
°C
°C
°C
KV
Operating Range
P ar am et er
Junction Temp erature Range
AVCC to GN D
PVCC to GN D
S y m b ol
T
J
AV
CC
PV
CC
M ax i m u m
-40 to +150
2.3 to 5.5
2.3 to AV
CC
Units
°C
V
V
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25
o
C and limits in boldface type apply over the full Operating Temperature Range
(T
J
= -40
o
C to +150
o
C). Unless otherwise specified, AV
CC
= PV
CC
= 2.5V, V
DDQ
= 2.5V.
P ar am et er
Reference Voltage
Load Regulation
(1)
S y m b ol
V
REF
REG
LOAD
V OS
V TT
I
Q
Te s t C o n d i t i o n s
I
REF_OUT
= 0mA
I
LOAD
: 0 to +1.5A
I
LOAD
: 0 to -1.5A
I
OUT
=0A , V
TT
- V
REF
I
LOAD
= 0A
Min
V DDQ/2
- 40mV
Ty p
1.25
-0.5
+0.5
M ax
V DDQ/2
+ 40mV
Units
V
%
V TT Outp ut Voltage Offset
Quiescent Current
AV CC Enab le Threshold
V DDQ Inp ut Imp edance
-20
0
400
2.1
+20
mV
µA
V
kΩ
Z
VDDQ
100
Note:
(1) For Load Regulation, use a 10ms current pulse width when measuring V
TT
.
©
2005 Semtech Corp.
2
www.semtech.com
SC2595
POWER MANAGEMENT
Pin Descriptions
(see Notes on page5).
PRELIMINARY
S O I C- 8L E DP
Pin #
1
2
3
M L P Q - 16
Pin #
1,3,4,6,9,-
13,16
2
5
P i n N am e
NC
GND
VSEN SE
N o internal connection.
(1)
Ground.
P i n Fu n c t i o n
V
SENSE
is a feedback pin. V
TT
plane is usually a narrow and long strip plane in most
m o t h e r b o ar d ap p l i cat i o n s. T h i s l o n g st r i p p l an e w i l l cau se a l ar g e t r ace
inductance and trace resistance. Consider the load transient condition; a fast
load current going through V
TT
strip plane can create voltage spikes on the V
TT
plane. The load current can also cause a DC voltage drop on the V
TT
plane. It is
recommen d ed th at V
SEN SE
sh ou l d b e con n ected to th e cen ter of V
TT
p l an e to
i mp rove th e l oad regu l ati on an d th e n oi se i mmu n i ty. In case th at on e can 't
connect the V
SENSE
pin to the center of the V
TT
plane, one should connect it to the
SC2595 V
TT
pin directly. A longer trace of V
SENSE
may pick up noise and cause the
error of load regulation; hence the longer trace must be avoided.
A 1u f t o 2.2u f cerami c cap aci t or cl ose t o t h e V
SE N SE
p i n i s req u i red t o avoi d
oscillation during transient condition.
V
REF
is an output pin, which provides the buffered output of the internal reference
voltage. System designer can use the V
REF
output voltage for N or thbridge chipset
an d memory. B ecau se th ese i n p u t p i n s are ty p i cal l y h i gh i mp ed an ce, th ere
should be a small amount of current drawn from the V
REF
pin [figure 9, 10]. To
improve the noise immunity, a ceramic capacitor (10nF - 100nF) should be added
from the V
REF
pin to ground with shor t distance.
The V
DDQ
pin is an input for creating internal reference voltage to regulate V
TT.
The
V
DDQ
voltage is connected to internal 50Kohm resistor divider. The central tap
of resistor divider (V
DDQ
/2) is connected to the internal voltage buffer, which output
is connected to V
REF
pin and the non-inver ting input of the error amplifier as the
reference voltage. With the feed b ack loop closed , the V
TT
outp ut voltage w ill
al w ay s track th e V
DDQ
/2 p reci sel y. It i s a recommen d ed th at a 1u F cerami c
capacitor should be added next to the V
DDQ
pin to increase the noise immunity.
The AV
CC
pin is used to supply all of the internal control circuitry. AV
CC
voltage has
to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2595
be in normal operation. If AV
CC
voltage is lower than the UVLO threshold voltage,
the V
TT
output voltage will remain at 0V.
The PV
CC
pin provides the rail voltage from where the V
TT
pin draws load current.
There is a limitation between AV
CC
and PV
CC
. The PV
CC
voltage must be less or
equal to AV
CC
voltage to ensure the correct output voltage regulation. The V
TT
source current capability is dependent on PV
CC
voltage. Higher the voltage on
PV
CC
, higher the source current; however, it will cause more power loss and higher
temperature rise [figure 5, 11, 12].
The V
TT
p in is the outp ut of SC2595. It can sink and source 1.5A continuous
c u r r e n t an d 3 A p e ak c u r r e n t w h i l e k e e p i n g e x c e l l e n t l o ad r e g u l at i o n . I t i s
recommended that one should use at least 220uF low ESR capacitors and 10uF
ceramic capacitors, which are uniformly spread on the V
TT
strip plane to reduce
the voltage spike under load transient condition.
4
www.semtech.com
4
7
V REF
5
8
VDDQ
(2)
6
10
AVCC
(2)
7
11,12
PVCC
(2)
8
14,15
V TT
©
2005 Semtech Corp.
京公网安备 11010802033920号
EEWORLD
