CYWUSB6935
WirelessUSB™ LR 2.4 GHz DSSS Radio
SoC
Features
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Low standby current < 1 µA
Integrated 30-bit Manufacturing ID
Operating voltage from 2.7 V to 3.6 V
Operating temperature from –40 °C to 85 °C
Offered in a small footprint 48 QFN
2.4-GHz radio transceiver
Operates in the unlicensed Industrial, Scientific, and Medical
(ISM) band (2.4 GHz to 2.483 GHz)
Receive sensitivity: –95 dBm
Up to 0 dBm output power
Range of up to 50 meters or more
Data throughput of up to 62.5 kbits/sec
Highly integrated low cost, minimal number of external compo-
nents required
Dual direct sequence spread spectrum (DSSS) reconfigurable
baseband correlators
SPI microcontroller interface (up to 2 MHz data rate)
13-MHz input clock operation
Functional Description
The CYWUSB6935 transceiver is a single-chip 2.4 GHz DSSS
Gaussian Frequency Shift Keying (GFSK) baseband modem
radio that connects directly to a microcontroller via a simple serial
peripheral interface.
Logic Block Diagram – CYWUSB6935
DIOV A L
DIO
SERDES
A
de
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IRQ
SS
SCK
MISO
MOSI
om
Digital
RESET
PD
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SERDES
B
m
DSSS
Baseband
A
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GFSK
Modulator
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The CYWUSB6935 is offered in an industrial temperature range
48-pin QFN and a commercial temperature range 48-pin QFN.
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RFOUT
DSSS
Baseband
B
GFSK
Demodulator
RFIN
N
X13IN
X13
X13OUT
ot
Synthesizer
Cypress Semiconductor Corporation
Document Number : 38-16008 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 05, 2010
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CYWUSB6935
Contents
Applications ...................................................................... 3
Applications Support ................................................... 3
Functional Overview ........................................................ 3
2.4 GHz Radio ............................................................. 3
GFSK Modem .............................................................. 3
Dual DSSS Baseband ................................................. 3
Serializer/Deserializer (SERDES) ............................... 4
Application Interfaces .................................................. 4
Clocking and Power Management .............................. 4
Receive Signal Strength Indicator (RSSI) ................... 4
Application Interfaces ...................................................... 4
SPI Interface ................................................................ 4
DIO Interface ............................................................... 6
Interrupts ..................................................................... 6
Application Examples ...................................................... 7
Register Descriptions ...................................................... 8
Absolute Maximum Ratings .......................................... 25
Operating Conditions ..................................................... 25
DC Characteristics
(Over the Operating Range) ............ 25
AC Characteristics ......................................................... 26
Radio Parameters ..................................................... 28
Power Management Timing ...................................... 29
Typical Operating Characteristics ............................. 30
Ordering Information ...................................................... 32
Ordering Code Definition ........................................... 32
Package Diagram ............................................................ 33
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC Solutions ......................................................... 36
Document Number : 38-16008 Rev. *G
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CYWUSB6935
Applications
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2.4 GHz Radio
The receiver and transmitter are a single-conversion, low-Inter-
mediate Frequency (low-IF) architecture with fully integrated IF
channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides an output power control range of 30 dB in seven steps.
Table 1. Internal PA Output Power Step Table
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
0
–2.4
–5.6
–9.7
–16.4
–20.8
–24.8
–29.0
Building/Home Automation
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Climate Control
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Lighting Control
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Smart Appliances
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On-Site Paging Systems
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Alarm and Security
Industrial Control
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Inventory Management
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Factory Automation
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Data Acquisition
Automatic Meter Reading (AMR)
Transportation
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Diagnostics
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Remote Keyless Entry
Consumer / PC
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Locator Alarms
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Presenter Tools
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Remote Controls
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Toys
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Applications Support
The CYWUSB6935 is supported by both the CY3632
WirelessUSB Development Kit and the CY3635 WirelessUSB
N:1 Development Kit. The CY3635 development kit provides all
of the materials and documents needed to cut the cord on multi-
point to point and point-to-point low bandwidth, high node density
applications including four small form-factor sensor boards and
a hub board that connects to WirelessUSB LR RF module
boards, a software application that graphically demonstrates the
multipoint to point protocol, comprehensive WirelessUSB
protocol code examples and all of the associated schematics,
gerber files and bill of materials. The WirelessUSB N:1 Devel-
opment Kit is also supported by the WirelessUSB Listener Tool.
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Functional Overview
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The CYWUSB6935 provides a complete SPI-to-antenna radio
modem. The CYWUSB6935 is designed to implement wireless
devices operating in the worldwide 2.4-GHz Industrial, Scientific,
and Medical (ISM) frequency band (2.400 GHz–2.4835 GHz). It
is intended for systems compliant with world-wide regulations
covered by ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1
V1.3.1 (European Countries); FCC CFR 47 Part 15 (USA and
Industry Canada) and ARIB STD-T66 (Japan).
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The CYWUSB6935 contains a 2.4-GHz radio transceiver, a
GFSK modem, and a dual DSSS reconfigurable baseband. The
radio and baseband are both code- and frequency-agile.
Forty-nine spreading codes selected for optimal performance
(Gold codes) are supported across 78 1-MHz channels yielding
a theoretical spectral capacity of 3822 channels. The
CYWUSB6935 supports a range of up to 50 meters or more.
Document Number : 38-16008 Rev. *G
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Both the receiver and transmitter integrated Voltage Controlled
Oscillator (VCO) and synthesizer have the agility to cover the
complete 2.4-GHz GFSK radio transmitter ISM band. The
synthesizer provides the frequency-hopping local oscillator for
the transmitter and receiver. The VCO loop filter is also
integrated on-chip.
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GFSK Modem
The transmitter uses a DSP-based vector modulator to convert
the 1-MHz chips to an accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM)
detector with automatic data slicer to demodulate the GFSK
signal.
Dual DSSS Baseband
Data is converted to DSSS chips by a digital spreader.
De-spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has three operating modes: 64-chips/bit
Single Channel, 32-chips/bit Single Channel, and 32-chips/bit
Single Channel Dual Data Rate (DDR).
64 Chips/Bit Single Channel
The baseband supports a single data stream operating at 15.625
kbits/sec. The advantage of selecting this mode is its ability to
tolerate a noisy environment. This is because the 15.625
kbits/sec data stream utilizes the longest PN Code resulting in
the highest probability for recovering packets over the air. This
mode can also be selected for systems requiring data transmis-
sions over longer ranges.
32 Chips/Bit Single Channel
The baseband supports a single data stream operating at 31.25
kbits/sec.
32 Chips/Bit Single Channel Dual Data Rate (DDR)
The baseband spreads bits in pairs and supports a single data
stream operating at 62.5 kbits/sec.
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CYWUSB6935
Serializer/Deserializer (SERDES)
CYWUSB6935 provides a data Serializer/Deserializer
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the SERDES
and receive bytes are read from the SERDES via the SPI
interface. The SERDES provides double buffering of transmit
and receive data. While one byte is being transmitted by the
radio the next byte can be written to the SERDES data register
insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the next
byte is received, at which time the old contents of the SERDES
data register will be overwritten.
reset for a new conversion until the receive mode is toggled off
and on. After a connection has been established, the RSSI
register can be read to determine the relative connection quality
of the channel. A RSSI register value lower than 10 indicates that
the received signal strength is low, a value greater than 28
indicates a strong signal level.
To check for a quiet channel before transmitting, first set up
receive mode properly and read the RSSI register (Reg 0x22). If
the valid bit is zero, then force the Carrier Detect register (Reg
0x2F, bit 7=1) to initiate an ADC conversion. Then, wait greater
than 50
μs
and read the RSSI register again. Next, clear the
Carrier Detect Register (Reg 0x2F, bit 7=0) and turn the receiver
OFF. Measuring the noise floor of a quiet channel is inherently a
'noisy' process so, for best results, this procedure should be
repeated several times (~20) to compute an average noise floor
level. A RSSI register value of 0-10 indicates a channel that is
relatively quiet. A RSSI register value greater than 10 indicates
the channel is probably being used. A RSSI register value
greater than 28 indicates the presence of a strong signal.
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Nominal frequency: 13 MHz
Operating mode: Fundamental mode
Resonance mode: Parallel resonant
Frequency stability: ±30 ppm
Series resistance: <100 ohms
Load capacitance: 10 pF
Drive level: 10
μW
to 100
μW
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Below are the requirements for the crystal to be directly
connected to X13IN and X13:
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A 13-MHz crystal is directly connected to X13IN and X13 without
the need for external capacitors. The CYWUSB6935 has a
programmable trim capability for adjusting the on-chip load
capacitance supplied to the crystal.
The radio frequency (RF) circuitry has on-chip decoupling capac-
itors. The CYWUSB6935 is powered from a 2.7-V to 3.6-V DC
supply. The CYWUSB6935 can be shut down to a fully static
state using the PD pin.
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Receive Signal Strength Indicator (RSSI)
The RSSI register (Reg 0x22) returns the relative signal strength
of the ON-channel signal power and can be used to:
1. Determine the connection quality
2. Determine the value of the noise floor
3. Check for a quiet channel before transmitting.
The internal RSSI voltage is sampled through a 5-bit
analog-to-digital converter (ADC). A state machine controls the
conversion process. Under normal conditions, the RSSI state
machine initiates a conversion when an ON-channel carrier is
detected and remains above the noise floor for over 50
μs.
The
conversion produces a 5-bit value in the RSSI register (Reg
0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22, bit
5). The state machine then remains in HALT mode and does not
Document Number : 38-16008 Rev. *G
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Clocking and Power Management
The CYWUSB6935 has a four-wire SPI communication interface
between an application MCU and one or more slave devices.
The SPI interface supports single-byte and multi-byte serial
transfers. The four-wire SPI communications interface consists
of Master Out-Slave In (MOSI), Master In-Slave Out (MISO),
Serial Clock (SCK), and Slave Select (SS).
The SPI receives SCK from an application MCU on the SCK pin.
Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active-low Slave Select (SS) pin must be asserted to initiate a
SPI transfer.
The application MCU can initiate a SPI data transfer via a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in
Figure 2
through
Figure 3.
The SS signal should not be
deasserted between bytes. The SPI communications interface is
as follows:
Command Direction (bit 7) = “0” Enables SPI read transaction.
A “1” enables SPI write transactions.
Command Increment (bit 6) = “1” Enables SPI auto address
increment. When set, the address field automatically incre-
ments at the end of each data byte in a burst access, otherwise
the same address is accessed.
Six bits of address.
Eight bits of data.
The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data bytes
as desired. A burst transaction is terminated by deasserting the
slave select (SS = 1). For burst read transactions, the application
MCU must abide by the timing shown in
Figure 11.
The SPI communications interface single read and burst read
sequences are shown in
Figure 1
and
Figure 2,
respectively.
The SPI communications interface single write and burst write
sequences are shown in
Figure 3
and
Figure 4,
respectively.
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An optional SERDES Bypass mode (DIO) is provided for appli-
cations that require a synchronous serial bit-oriented data path.
This interface is for data only.
Application Interfaces
SPI Interface
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CYWUSB6935 has a fully synchronous SPI slave interface for
connectivity to the application MCU. Configuration and
byte-oriented data transfer can be performed over this interface.
An interrupt is provided to trigger real time events.
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Application Interfaces
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CYWUSB6935
Table 2. SPI Transaction Format
Byte 1
Bit #
Bit Name
7
DIR
6
INC
[5:0]
Address
Figure 1. SPI Single Read Sequence
SCK
SS
cm d
MOSI
M IS O
D IR
Byte 1+N
[7:0]
Data
addr
A5
A4
A3
A2
A1
A0
0
IN C
0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. SPI Burst Read Sequence
SS
cm d
MOSI
M IS O
D IR
0
IN C
1
A5
A4
A3
A2
A1
A0
d a ta to m c u
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addr
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1
D1
D0
D7
SCK
ew
d a ta to m c u
D6
D5
D4
D3
D2
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1+N
D1
D0
de
D7
D6
D5
D4
D3
D2
Figure 3. SPI Single Write Sequence
SS
cm d
M O SI
M ISO
DIR
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SCK
N
1
ot
addr
A3
A2
A1
A0
D7
om
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INC
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data from m cu
D6
D5
D4
D3
D2
D1
D0
A5
A4
Figure 4. SPI Burst Write Sequence
SCK
SS
cm d
MOSI
M IS O
D IR
a dd r
A5
A4
A3
A2
A1
A0
D7
d ata fro m m cu
D6
D5
D4
D3
D2
1
D1
D0
D7
da ta from m cu
D6
D5
D4
D3
D2
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D1
D0
1
IN C
1
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