Application Report
SCHA004 - October 2002
Understanding Buffered and Unbuffered CD4xxxB Series
Device Characteristics
R. E. Funk
ABSTRACT
Both buffered and unbuffered CMOS B-series gates, inverters, and high-current IC products
are available from TI. Each product classification has application advantages in appropriate
logic-system designs. Many CMOS suppliers have concentrated on promoting buffered
B-series products, with applications literature focusing on the attributes and use of the
buffered types. This practice has left an imbalance in the understanding and application of
both buffered and unbuffered gates. In some instances, customers are not using unbuffered
products when they are the best choice for the intended application. This application report
offers clarification of the relative merits of the buffered and unbuffered CMOS devices.
This application report was acquired by TI from Harris Semiconductor Corporation and edited
and reformatted in December 2001. This application report is adapted from AN6558.1,
published by Harris (1992), which, in turn, was adapted from ICAN-6558, published by RCA
(1983).
Standard Linear & Logic
Contents
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Buffered CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Unbuffered CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Gain and Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Oscillation for Slow Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Applications Guidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TI Gate, Inverter, and Driver Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks are the property of their respective owners.
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List of Figures
1
2
3
4
5
6
7
8
9
10
11
Buffered (CD4001B) and Unbuffered (CD4001UB) Two-Input NOR Gates . . . . . . . . . . . . . . . . . . . . 4
Schematic Diagrams of Buffered and Unbuffered Two-Input NOR Gates . . . . . . . . . . . . . . . . . . . . . 5
Constant Output Impedance of Buffered Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Variable Output Impedance of Unbuffered Two-Input NOR Gate
(The Resistors Represent the ON Impedance of a p- or n-Channel MOS Transistor) . . . . . . . . . . . 7
Voltage Transfer Characteristics of Buffered Two-Input NOR Gate (CD4001B) . . . . . . . . . . . . . . . . 8
Voltage Transfer Characteristics of Unbuffered Two-Input NOR Gate (CD4001UB)
With Output Voltages of 5 V and 15 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Linear-Gain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Linear-Mode Gain of Buffered and Unbuffered Two-Input NOR Gates . . . . . . . . . . . . . . . . 13
Buffered Output Oscillation for Slow Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Capacitance of Buffered Two-Input NOR Gate (CD4001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Capacitance of Unbuffered Two-Input NOR Gate (CD4001UB) . . . . . . . . . . . . . . . . . . . . . . . . 15
List of Tables
1
2
3
4
5
Comparison of Buffered and Unbuffered Gate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Characteristics of Buffered and Unbuffered Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input-Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications of Buffered and Unbuffered CMOS Gates and Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TI COS/MOS Buffered and Unbuffered Gate, Inverter, and Driver Types . . . . . . . . . . . . . . . . . . . . . . . 16
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Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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Background
Historically, most CMOS gates, inverters, and high-current IC products were unbuffered and
exhibited good logic-system performance, speed, noise immunity, and quasi-linear
characteristics in a wide variety of applications. As the scope of CMOS products broadened and
additional manufacturers began making them, buffered gate and inverter products became
available. While initial buffered products were confined to OR and AND functions, buffered NOR
and NAND gates were introduced with the same generic 4000A-series designations as the
original, widely used, unbuffered gates. Users were surprised by the noninterchangeability of the
devices in applications where speed, noise immunity, output impedance, and linear
gain-bandwidth characteristics were critical. It is of benefit to CMOS users to have available the
definitions and designations of both buffered and unbuffered B-series CMOS devices as
determined by the JEDEC CMOS Standardizing Committee under the cognizance of the JC40.2
JEDEC Committee of EIA. The official JEDEC definitions are repeated in the following
paragraphs, along with detailed explanations and examples. Comparisons of user-oriented
characteristics and the use of buffered and unbuffered gates are also reviewed.
Definitions
Buffered CMOS
A buffered CMOS device is one for which the output ON impedance is independent of any and
all valid input logic conditions, both preceding and present, and is said to have a buffered output
or to be a buffered CMOS device. All such products are designated by the suffix B.
Unbuffered CMOS
Devices that meet B-series specifications, except that the logical outputs are not buffered and
the V
IL
and V
IH
specifications are 20% and 80% of V
DD
, respectively, are marked with the UB
designation, including (but not limited to) 4001UB, 4007UB, 4009UB, 4011UB, 4041UB,
4049UB, and 4069UB.
The official JEDEC definitions are applicable primarily to gates, inverters, and high-current
(inverting) drivers, such as the specific UB types listed previously. Noninverting gates and
drivers, as well as all medium-scale integrated circuit (MSI) and large-scale integrated circuit
(LSI B) types are, by definition, B types. There are special analog I/O types that also are B types
because they conform to all B standards, except that they have special analog I/O circuitry.
Examples of parts that have no buffered or unbuffered significance are 4016B, 4046B, 4051B,
4052B, 4053B, 4067B, 4097B, 4066B, 4511B, and 4528B.
Logic examples of the buffered and unbuffered two-input NOR gates are shown in Figure 1.
Note that the buffered logic can be implemented by either a two-input NOR function, followed by
two inverters or by two input inverters, followed by the two-input NAND gate and an output
buffer. TI uses the latter logic configuration, which has the advantage of optimizing device noise
immunity by negating the effect of stacked devices at the input. This characteristic is especially
significant for three- or four-input gates where three or four PMOS or NMOS transistors are
stacked in series at the input. In this case, the inputs have an effective offset in threshold and
reduced input noise immunity.
Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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A
Output
B
OR
A
Output
B
(a) Buffered – CD4001B
A
B
Output
(b) Unbuffered – CD4001UB
92CS-28330
Figure 1. Buffered (CD4001B) and Unbuffered (CD4001UB) Two-Input NOR Gates
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Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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Figure 2 is a schematic representation of the TI buffered and unbuffered two-input NOR gates.
The improved four-diode-input gate-oxide protection circuit is shown at the inputs.
VDD
VDD
VDD
VDD
A
Output
VSS
VDD
VSS
VDD
VSS
VSS
B
VSS
VSS
(a) Buffered
VDD
VDD
A
VSS
VDD
Output
B
VSS
VSS
(b) Unbuffered
92CS-28331
Figure 2. Schematic Diagrams of Buffered and Unbuffered Two-Input NOR Gates
Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
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