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IBM0436A81QLAB-3N

Description
Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA119, BGA-119
Categorystorage    storage   
File Size142KB,26 Pages
ManufacturerIBM
Websitehttp://www.ibm.com
Download Datasheet Parametric View All

IBM0436A81QLAB-3N Overview

Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA119, BGA-119

IBM0436A81QLAB-3N Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIBM
Parts packaging codeBGA
package instructionBGA, BGA119,7X17,50
Contacts119
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time1.8 ns
I/O typeCOMMON
JESD-30 codeR-PBGA-B119
JESD-609 codee0
length22 mm
memory density9437184 bit
Memory IC TypeSTANDARD SRAM
memory width36
Number of functions1
Number of terminals119
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize256KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA119,7X17,50
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5,3.3 V
Certification statusNot Qualified
Maximum seat height2.679 mm
Maximum standby current0.1 A
Minimum standby current3.14 V
Maximum slew rate0.435 mA
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
.
IBM0418A81QLAB
IBM0418A41QLAB
IBM0436A81QLAB
IBM0436A41QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Single Differential Extended HSTL Clock
• +3.3V Power Supply, Ground, 1.5V V
DDQ
, and
0.75V V
REF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Registered Outputs
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability and Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs—IBM0436A41QLAB,
IBM0418A41QLAB, IBM0418A81QLAB, and
IBM0436A81QLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O,
and can achieve 3.0ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the next rising edge of the K clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interfaces.
crrh3316.08
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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