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STM32F030R8: DescriptionValue-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation; File Size7MB，779 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM32F030R8 Overview

Value-line ARM-based 32-bit MCU with 16 to 64-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation

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RM0360

Reference manual

STM32F030x4/x6/x8/xC and STM32F070x6/xB

advanced ARM

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontroller memory and

peripherals.

It applies to STM32F030x4/x6/x8/xC and STM32F070x6/xB devices.

For the purpose of this manual, STM32F030x4/x6/x8/xC and STM32F070x6/xB

microcontrollers are referred to as STM32F0x0.

The STM32F0x0 is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics, please refer to

the corresponding datasheet.

For information on the ARM

Cortex

-M0 core, please refer to the

ARM

Cortex

-M0

technical reference manual.

Related documents



ARM

Cortex

-M0 technical reference manual, available from ARM website at

www.arm.com



STM32F0xx Cortex-M0 programming manual (PM0215)



STM32F030x4/x6/x8/xC and STM32F070x6/xB datasheets available from

STMicroelectronics website at

www.st.com

April 2017

DocID025023 Rev 4

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www.st.com

Contents

RM0360

Contents

Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.1

1.2

1.3

List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.1

2.2

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.1

2.2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 37

2.3

2.4

2.5

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.1

3.2

Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2.1

3.2.2

Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Option byte write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.1

3.3.2

3.3.3

3.4

3.5

Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.5.1

3.5.2

3.5.3

3.5.4

3.5.5

3.5.6

3.5.7

3.5.8

Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 58

Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 59

Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Flash Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . 62

Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 63

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Contents

Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.1

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.1.1

4.1.2

4.1.3

4.1.4

User and read protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

User data option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Write protection option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Option byte map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 69

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.1

5.3.2

5.3.3

CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 72

Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.4

CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.1

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.1.1

6.1.2

Independent A/D converter supply and reference voltage . . . . . . . . . . . 75

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 76

Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

RTC wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.2

6.3

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.1

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Contents

RM0360

6.4

Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4.1

6.4.2

6.4.3

Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 85

PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.1

7.1.2

7.1.3

Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Independent watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Internal/external clock measurement with TIM14 . . . . . . . . . . . . . . . . . 97

7.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

7.2.11

7.2.12

7.3

7.4

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.8

7.4.9

7.4.10

7.4.11

7.4.12

Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101

Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

APB peripheral reset register 2 (RCC_APB2RSTR) . . . . . . . . . . . . . . 106

APB peripheral reset register 1 (RCC_APB1RSTR) . . . . . . . . . . . . . . 108

AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 111

APB peripheral clock enable register 2 (RCC_APB2ENR) . . . . . . . . . 112

APB peripheral clock enable register 1 (RCC_APB1ENR) . . . . . . . . . 114

RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 117

Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 120

Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 122

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7.4.13

7.4.14

7.4.15

Contents

Clock configuration register 3 (RCC_CFGR3) . . . . . . . . . . . . . . . . . . . 123

Clock control register 2 (RCC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 123

RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.3.12

8.3.13

8.3.14

General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 129

I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 135

Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 135

GPIO port mode register (GPIOx_MODER) (x =A..D, F) . . . . . . . . . . . 136

GPIO port output type register (GPIOx_OTYPER) (x = A..D, F) . . . . . 136

GPIO port output speed register (GPIOx_OSPEEDR)

(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A..,D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

GPIO port input data register (GPIOx_IDR) (x = A..D, F) . . . . . . . . . . 138

GPIO port output data register (GPIOx_ODR) (x = A..D, F) . . . . . . . . 138

GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F) . . . . . . . 138

GPIO port configuration lock register (GPIOx_LCKR)

(x = A..B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

GPIO alternate function low register (GPIOx_AFRL)



(x = A..D, ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

GPIO alternate function high register (GPIOx_AFRH)

(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.4

GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

8.4.9

8.4.10

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	STM32F030R8	STM32F030C8	STM32F030F4	STM32F030K6	STM32F030x4	STM32F030x6	STM32F030x8
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Today at 10:00 AM, live broadcast with awards: ADI's technologies and products in China's energy internet applications: Today at 10:00 AM, live broadcast with awards: ADI's technologies and products in China's energy internet applicationsClick here to enter the live broadcastLive broadcast time: 10:00-11:30 am, January...; EEWORLD社区 Integrated technical exchanges

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