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2305-1DCGI

Description
2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
Categorysemiconductor    logic   
File Size178KB,12 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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2305-1DCGI Overview

2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

2305-1DCGI Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals8
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
Processing package descriptionGREEN, SOIC-8
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE TIN
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
series2305
Output characteristics3-ST
Enter conditionsSTANDARD
Logic IC typePLL BASED CLOCK DRIVER
Number of inverted outputs0.0
Real output number4
propagation delay TPD0.3500 ns
Maximum same-side bending0.2500 ns
Max-Min frequency133 MHz
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
FEATURES:
IDT2305
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT2305-1 for Standard Drive
IDT2305-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Power down mode
Available in SOIC/TSSOP packages
DESCRIPTION:
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25
µA,
the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
PLL
REF
1
Control
Logic
3
CLK1
2
CLK2
5
CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2009
Integrated Device Technology, Inc.
AUGUST 2009
DSC 5174/8

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Number of functions 1 1 1 1 1 1 1
Number of terminals 8 8 8 8 8 8 8
Maximum operating temperature 85 Cel 70 Cel 70 Cel 70 Cel 70 Cel 70 Cel 70 Cel
Minimum operating temperature -40 Cel 0.0 Cel 0.0 Cel 0.0 Cel 0.0 Cel 0.0 Cel 0.0 Cel
Maximum supply/operating voltage 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply/operating voltage 3 V 3 V 3 V 3 V 3 V 3 V 3 V
Rated supply voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Processing package description GREEN, SOIC-8 GREEN, SOIC-8 GREEN, SOIC-8 GREEN, SOIC-8 GREEN, SOIC-8 GREEN, SOIC-8 GREEN, SOIC-8
Lead-free Yes Yes Yes Yes Yes Yes Yes
EU RoHS regulations Yes Yes Yes Yes Yes Yes Yes
state ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
packaging shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package Size SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
surface mount Yes Yes Yes Yes Yes Yes Yes
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal spacing 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
terminal coating MATTE TIN MATTE TIN MATTE TIN MATTE TIN MATTE TIN MATTE TIN MATTE TIN
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Packaging Materials PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Temperature level INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
series 2305 2305 2305 2305 2305 2305 2305
Output characteristics 3-ST 3-ST 3-ST 3-ST 3-ST 3-ST 3-ST
Enter conditions STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD
Logic IC type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of inverted outputs 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Real output number 4 4 4 4 4 4 4
propagation delay TPD 0.3500 ns 0.3500 ns 0.3500 ns 0.3500 ns 0.3500 ns 0.3500 ns 0.3500 ns
Maximum same-side bending 0.2500 ns 0.2500 ns 0.2500 ns 0.2500 ns 0.2500 ns 0.2500 ns 0.2500 ns
Max-Min frequency 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
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