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854S006AGILF

Description
854S SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Categorysemiconductor    logic   
File Size672KB,17 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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854S006AGILF Overview

854S SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24

854S006AGILF Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals24
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage2.62 V
Minimum supply/operating voltage2.38 V
Rated supply voltage2.5 V
Processing package description4.40 × 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
packaging shapeRectangle
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6500 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
series854S
Enter conditionsdifferential
Logic IC typeLow Skew Clock Driver
Number of inverted outputs0.0
Real output number6
propagation delay TPD0.8500 ns
Maximum same-side bending0.0550 ns
Low Skew, 1-to-6,
Differential-to-LVDS Fanout Buffer
Datasheet
854S006
Description
The 854S006 is a low skew, high performance 1-to-6,
Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept
most standard differential input levels. The 854S006 is
characterized to operate from either a 2.5V or a 3.3V power
supply.
Guaranteed output and part-to-part skew characteristics
make the
854S006
ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
CLK
nCLK
Pull-up
Pull-down
Pin Assignment
nCLK
CLK
V
DD
V
DDO
Q0
nQ0
GND
Q1
nQ1
V
DDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
GND
V
DD
V
DDO
nQ5
Q5
GND
nQ4
Q4
V
DDO
nQ3
Q3
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
©2017 Integrated Device Technology, Inc.
1
April 11, 2017

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854S006AGILF ICS854S006AGILF
Description 854S SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 IC,1:6 OUTPUT, DIFFERENTIAL,TSSOP,24PIN,PLASTIC
Lead-free Yes Yes
EU RoHS regulations Yes Yes
state ACTIVE CONSULT MFR
terminal coating MATTE Tin MATTE Tin
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