LVCMOS/LVTTL-TO-DIFFERENTIAL
3.3V, 2.5V LVPECL TRANSLATOR
ICS85320I
G
ENERAL
D
ESCRIPTION
The ICS85320I is a LVCMOS / LVTTL-to-Differen-
tial 3.3V, 2.5V LVPECL translator and a member
HiPerClockS™
of the HiPerClocks™ family of High Performance
Clocks Solutions from IDT. The ICS85320I has a
single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels and translates
them to 3.3V or 2.5V LVPECL levels. The small outline 8-pin
SOIC package makes this device ideal for applications where
space, high performance and low power are important.
F
EATURES
•
One differential 2.5V/3.3V LVPECL output
•
LVCMOS/LVTTL CLK input
•
CLK accepts the following input levels: LVCMOS or LVTTL
•
Maximum output frequency: 267MHz
•
Part-to-part skew: 275ps (maximum)
•
Additive phase jitter, RMS: 0.05ps (typical)
•
3.3V operating supply voltage
(operating range 3.135V to 3.465V)
•
2.5V operating supply voltage
(operating range 2.375V to 2.625V)
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
CLK
Q
nQ
P
IN
A
SSIGNMENT
nc
Q
nQ
nc
1
2
3
4
8
7
6
5
V
CC
CLK
nc
V
EE
ICS85320I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
IDT
™
/ ICS
™
3.3V, 2.5V LVPECL TRANSLATOR
1
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 4, 6
2,3
5
7
8
Name
nc
Q, nQ
V
EE
CLK
V
CC
Type
Unused
Output
Power
Input
Power
Pullup
Description
No connect.
Differential output pair. LVPECL interface levels.
Negative supply pin.
LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT
™
/ ICS
™
3.3V, 2.5V LVPECL TRANSLATOR
2
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
112.7°C/W (0 lfpm)
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
25
Units
V
V
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
CLK
CLK
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
1.3
5
Units
V
V
µA
µA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
CL K
CLK
V
CC
= V
IN
= 2.625V
V
CC
= V
IN
= 2.625V
-150
Test Conditions
Minimum
1.6
-0.3
Typical
Maximum
V
CC
+ 0.3
0.9
5
Units
V
V
µA
µA
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
IDT
™
/ ICS
™
3.3V, 2.5V LVPECL TRANSLATOR
3
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
T
ABLE
4A. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
ƒ
≤
267MHz
Integration Range:
12KHz - 20MHz
20% to 80%
0.8
0.05
275
200
700
Test Conditions
Minimum
Typical
Maximum
267
1.4
Units
MHz
ns
ps
ps
ps
t
jit
t
sk(pp)
t
R
, t
F
odc
Output Duty Cycle
45
55
%
NOTE 1: Measured from V
CC
/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
ƒ
≤
267MHz
Integration Range:
12KHz - 20MHz
20% to 80%
0. 8
0.05
375
200
700
Test Conditions
Minimum
Typical
Maximum
215
1. 7
Units
MHz
ns
ps
ps
ps
t
jit
t
sk(pp)
t
R
, t
F
odc
Output Duty Cycle
45
55
%
NOTE 1: Measured from V
CC
/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
3.3V, 2.5V LVPECL TRANSLATOR
4
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
-20
-30
-40
-50
-60
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
@ 156.25MHz (12KHz to 20MHz)
= 0.05ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT
™
/ ICS
™
3.3V, 2.5V LVPECL TRANSLATOR
5
ICS8532AMI REV A NOVEMBER 13, 2006
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