ST72F325AR7TAX datasheet, PDF - EEWORLD Datasheet

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ST72F325AR7TAX: Description8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，243 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ST72F325AR7TAX Overview

8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

ST72F325AR7TAX Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	unknown
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G64
length	10 mm
Number of I/O lines	48
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72325xxx-Auto

8-bit MCU for automotive with 16 to 60 Kbyte Flash, ADC,

CSS, 5 timers, SPI, SCI, I2C interface

Features

■

Memories

– 16 to 60 Kbyte dual voltage High Density

Flash (HDFlash) with readout protection

capability. In-application programming and

in-circuit programming for HDFlash devices

– 512 to 2048 bytes RAM

– HDFlash endurance: 100 cycles, data

retention 20 years

Clock, reset and supply management

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and

bypass for external clock

– PLL for 2x frequency multiplication

– 4 power saving modes: Halt, Active Halt,

Wait and Slow

– Clock security system

LQFP32

7x7

LQFP44

10 x 10

LQFP64

10 x 10

LQFP64

14 x 14

■

– Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1

timer, PWM and pulse generator modes

– 8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

■

Interrupt management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– Top Level Interrupt (TLI) pin on 64-pin

devices

– 9/6 external interrupt lines (on 4 vectors)

1 analog peripheral (low current coupling)

– 10-bit ADC with up to 16 input ports

Up to 48 I/O ports

– 48/32/24 multifunctional bidirectional I/O

lines

– 34/22/17 alternate function lines

– 16/12/10 high sink outputs

■

-O

■

3 communications interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface

– I

C multimaster interface

Instruction set

– 8-bit data manipulation

– 63 basic instructions

– 17 main addressing modes

– 8x8 unsigned multiply instruction

Development tools

– Full hardware/software development

package

– DM (debug module)

Device summary

Part number

Table 1.

Reference

5 timers

– Main clock controller with Real-time base,

Beep and Clock-out capabilities

– Configurable watchdog timer

ST72325K4-Auto, ST72325K6-Auto,

ST72325J4-Auto, ST72325J6-Auto,

ST72325xxx- ST72325J7-Auto, ST72325J9-Auto,

Auto

ST72325AR6-Auto, ST72325R6-Auto,

ST72325AR7-Auto, ST72325R7-Auto,

ST72325AR9-Auto, ST72325R9-Auto

August 2010

Doc ID 13770 Rev 3

1/243

www.st.com

Contents

ST72325xxx-Auto

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1

2.2

Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.1

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.2

5.3.3

5.3.4

5.3.5

6.1

6.2

6.3

-O

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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Contents

6.4

6.5

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 46

Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

6.6.6

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 52

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.1

7.2

7.3

7.4

7.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.5.1

7.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 59

7.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.6.1

7.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 63

8.1

8.2

8.3

8.4

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.4.1

8.4.2

Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

-O

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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Contents

ST72325xxx-Auto

9.1

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.3

9.4

9.5

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 84

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.9.1

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Main clock controller with real-time clock and beeper (MCC/RTC) . . 86

11.1

11.2

11.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.8.1

11.8.2

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 88

MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.5

11.6

11.7

11.8

11.4

-O

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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Contents

12.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

12.2.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 94

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 94

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.3

ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . 100

Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.1

13.2

13.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3.1

13.3.2

13.3.3

13.3.4

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

13.4

13.5

13.6

13.7

13.3.5

13.3.6

13.3.7

-O

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

13.7.1

13.7.2

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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Design of wireless data acquisition system based on Bluetooth technology: Abstract: A Bluetooth wireless data acquisition system with a master-slave network structure is established using Bluetooth technology. The design uses a Bluetooth module based on the BC219159 Bluetoo...; 吸铁石上 RF/Wirelessly

Simulation Design of Single-Phase Boost Rectifier Circuit: Hello everyone. The teacher asked me to make a single-phase Boost rectifier circuit. Since my undergraduate major is thermal energy and power engineering, I came here for help. I found a related paper...; dreamtime Analog electronics

Basic knowledge of electronic theory 3: Basic knowledge of electronic theory...; awnuaw Embedded System

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