BU-65528 and BU-65527
MIL-STD-1553B BC/RT/MT
VME/VXI INTERFACE UNIT
BU-65528
BU-65527M
DESCRIPTION
The BU-65528 and BU-65527 pro-
vide full, intelligent interfacing
between multiple dual-redundant
MIL-STD-1553A/B Notice 2 Data
Buses and parallel VMEbus and
VXIbus. Software controls the opera-
tion of each independent channel of
the BU-65528 as either a MIL-STD-
1553 Bus Controller (BC), Remote
Terminal (RT), or Bus Monitor
Terminal (MT). The BU-65527M is a
militarized version of the BU-65528M
card which is conduction-cooled as
per IEEE 1101.2. The BU-65527C
card is similar to the BU-65528 card
except it is air-cooled and contains no
wedge locks. In addition, the BU-
65527C and BU-65527M access the
1553 bus through the standard P2
connector (refer to the mechanical
outline figures for details).
The BU-65528 and BU-65527 imple-
ment each dual-redundant 1553 inter-
face through the use of DDC's BU-
61586 and BU-61585 Advanced
Communication Engine (ACE) com-
ponents, respectively.
The BU-65528 /27 may be configured
with one, two, three, or four ACE com-
ponents, providing an option to inter-
face with up to four independent 1553
buses using a single double eurocard
(VXI B size card).
Each 1553 channel contains 12K x 16
of on-board RAM. The shared RAM is
fully double buffered, preventing par-
tially updated data from being read by
the VME/VXI host or transmitted to
the 1553 data bus.
Each mode of operation (BC, RT, and
MT) implements sophisticated data
buffering structures which reduce the
real-time software requirements and
off-load the host processor.
The BC mode's frame auto-repeat
option and programmable intermes-
sage gap time provide a simple mech-
anism for controlling the repetitive tim-
ing of 1553 messages. Other BC fea-
tures include automatic retries, flexi-
ble support of 1553A devices, and
programmable response timeout.
FEATURES
•
VMEbus/VXIbus Interface
•
Multiprotocol Support of MIL-STD-
1553A and B Notice 2.
•
Commercial and Militarized
Versions Available
•
Programmable BC Gap Times
•
BC Frame Auto-Repeat
•
Automatic BC Retries
•
Flexible RT Data Buffering
•
Selective Message Monitor
•
Simultaneous RT/Monitor Mode
•
12K x 16 Shared RAM
•
Flexible Interrupt Generation
•
Comprehensive Self-Test
Capability
D15-D1
BUFFER
A15-A1
BUFFER
DATA
ADDRESS
VME
or
VXI
BUS
DS0
DS1
AS
IRQ7-IRQ1
IACK
IACK IN
IACK OUT
DTACK
RD/WR
SYS RESET
MOD ID
AM5-AM0
CONTROL LOGIC,
ADDRESS DECODING,
ID REGISTER,
STATUS/CONTROL
REGISTER,
OFFSET REGISTER,
VECTOR/LEVEL
REGISTER
BU-61585
or
BU-61586
ACE
BC/RT/MT
Channel #1
Ch. #4
Ch. #3
Ch. #2
FIGURE 1. BU-65528 AND BU-65527 BLOCK DIAGRAM
©
1999, 1995 Data Device Corporation
TABLE 1. BU-65528/27 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
+5 V Supply Voltage
-12 V Supply Voltage
RECEIVER
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35
Ω,
Measured on Bus
!
Transformer Coupled,
Measured on Stub
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Direct
Coupled Across 35 ohms
Rise/Fall Time
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
!
+5 V
!
-12 V
Current Drain (Note 1)
!
BU-65528/27X1
• +5V
• -12V
• Idle
• 25% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65528/27X2
• +5V
• -12V
• Idle
• 25% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65528/27X3
• +5V
• -12V
• Idle
• 25% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65528/27X4
• +5V
• -12V
• Idle
• 25% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
(Note 1)
BU-65528/27X1
!
Idle
!
25% Transmitter Duty Cycle
!
100% Transmitter Duty Cycle
BU-65528/27X2
!
Idle
!
25% Transmitter Duty Cycle
!
100% Transmitter Duty Cycle
BU-65528/27X3
!
Idle
!
25% Transmitter Duty Cycle
!
100% Transmitter Duty Cycle
BU-65528/27X4
!
Idle
!
25% Transmitter Duty Cycle
!
100% Transmitter Duty Cycle
MIN
-0.3
-18
TYP
MAX
7.0
+0.3
0.860
10
UNITS
V
V
Vp-p
Vpeak
TABLE 1. BU-65528/27 SPECIFICATIONS
PARAMETER
1553 MESSAGE TIMING
RT Response Time
Completion of CPU Write (BC Start-
to-Start of First BC Message)
BC Intermessage Gap (Note 2)
BC/RT/MT Response Timeout
(Note 3)
!
18.5 nominal
!
22.5 nominal
!
50.5 nominal
!
128.0 nominal
Transmitter Watchdog Timeout
ENVIRONMENTAL
BU-65528, BU-65527C
Operating component temperature
(ambient)
Storage temperature
BU-65527M
Operating temperature (measured
at the card guides)
Maximum component junction
temperatures
Storage Temperature
Vibration
Shock
Operating Humidity
Non-operating Humidity
PHYSICAL CHARACTERISTICS
Size
!
“B” Size
Weight
!
BU-65528, BU-65527C
!
BU-65527M
MIN
4
2.5
9.5
TYP
MAX
7
UNITS
µs
µs
µs
19.5
23.5
51.5
131
µs
µs
µs
µs
µs
6
18
7
20
9
27
10
Vp-p
Vp-p
mVp-p,
diff
mV
nsec
17.5
21.5
49.5
127
18.5
22.5
50.5
130
668
-90
100
150
90
300
0
-20
-55
+70
+85
+85
+130
°C
°C
°C
°C
°C
4.5
-12.6
5.5
-11.4
V
V
-55
+125
600
30
80
230
0.8
60
160
460
0.9
90
160
460
1.2
0.120
0.320
0.920
823
60
108
255
1.06
120
216
510
1.47
180
216
510
1.71
0.24
0.43
1.02
mA
mA
mA
mA
A
mA
mA
mA
A
mA
mA
mA
A
A
A
A
Random vibration, 0.1 g
2
/ Hz
from 20 Hz to 2000 Hz
40g, 11ms, half sine
0 to 95% non-condensing
100% condensing
6.3 x 9.2 x 0.6
(160 x 233.7 x 15.2)
13.5
(383.1)
20
(567)
in.
(mm)
0z.
(gm)
Oz.
(gm)
Notes:
(1) Assumes all installed 1553 channels (1, 2, 3, or 4) on card are
transmitting at the specified duty cycle on only one of the dual-redun-
dant MIL-STD-1553A/B Notice 2 data buses.
(2) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535
µs
minus message time), in
increments of 1
µs.
(3) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
3.4
3.7
4.5
4.7
5.3
7.0
5.6
6.4
9.0
7.4
8.6
12.0
4.8
5.1
5.9
6.8
7.3
8.9
9.5
10.3
12.8
11.5
12.5
15.8
W
W
W
W
W
W
W
W
W
W
W
W
FUNCTIONAL OVERVIEW
GENERAL (REFERENCE BLOCK DIAGRAM FIGURE 1)
The BU-65528/27 provides a user-friendly interface between
multiple serial MIL-STD-1553 Buses and the VME/VXI bus. The
interface to each 1553 bus is implemented through the use of a
BU-61586 Advanced Communication Engine (ACE) component
(BU-61585 ACE used on BU-65527). The board has the option
for one, two, three, or four ACE components, providing the capa-
bility of interfacing with up to four independent 1553 buses.
Data Device Corporation
www.ddc-web.com
2
BU-65528 and BU-65527
F1 web-10/02-0
The software interface of each 1553 channel is completely inde-
pendent of the other channels. The operating modes of each of
the BU-65528/27's 1553 channels are controlled through the use
of 30 on-board registers. 1553 message traffic is stored and
retrieved using 12K of shared, memory mapped, on-board RAM.
The 1553 internal registers control and operate the BU-
65528/27. They include the Configuration Registers, Start/Reset
Register, 1553 Time Tag Register, Interrupt Select Register, and
RT Address Register. The Configuration Registers define the
operating mode and various options. The Start/Reset Register
provides reset and BC/MT start signals. The Interrupt Mask
Register enables desired interrupts, with the interrupt priority
level being software programmable by the user.
The RT Address Register is programmed in Configuration
Register #5. The 1553 Time Tag Register is used to time tag
messages in BC, RT and MT modes. The VME/VXI functions are
controlled by the other six registers which include the
Identification Register, Device Type, Status/Control, Offset,
Vector/Enable/Level, and Device Type Extension registers.
The BU-65528/27's 12K x 16 of static RAM is shared by the CPU
and the 1553 Bus with memory arbitration handled automatical-
ly by the BU-65528/27.
The BU-65528/27 will withhold the
DTACK
signal to the VME/VXI
backplane while a word is being transferred to or from the 1553
Bus. Since the memory arbitration is handled by simply stretch-
ing the handshake cycle, the wait state is transparent to the
CPU's software. A maximum wait of 2.5
µs
can occur.
In addition to storing the 1553 message data, the RAM imple-
ments the Stacks and Lookup Tables required for the different
modes of operation. A Descriptor Stack is used in both BC, RT
and MT modes. This stack records the status of each message,
the time the message was transmitted or received, and contains
either the received 1553 command (in RT and MT mode), or the
actual address of the 1553 message block (in BC mode). In RT
mode, a Lookup Table is provided to define the addresses of the
data blocks to be used when receiving or transmitting messages
for the individual subaddresses. In MT mode a separate data
stack is used to store the remainder of the message.
addressing. Contact factory for version configured for VME
Extended (A32) addressing.
The RT address of each 1553 channel on the BU-65527M is
selected through dedicated pins on the VME P2 connector. A
hardwired RT address ensures the integrity of the address and
precludes the possibility of errant software programming the
wrong RT address which could effect the operation of other ter-
minals on the 1553 bus.
Both the BU-65527X and BU-65528 are implemented with ACE
components. As such the BU-65527X is fully software compati-
ble with the BU-65528 with the only exception being the pro-
gramming of the RT address (BU-65528 RT address is latchable
while the BU-65527X RT address is hardwired through the P2
connector). The BU-65527X utilizes DDC's BU-61585 ACE com-
ponent while the BU-65528 utilizes DDC's BU-61586 ACE com-
ponent.
MEMORY MANAGEMENT
The BU-65528/27 incorporates complete memory management
and processor interface logic. The software interface to the host
processor is implemented by means of on-board registers plus
12K words of RAM. For all three modes, a stack area of RAM is
maintained. In BC mode, the stack allows for the scheduling of
multi-message frames. For all three modes, the stack provides a
real-time chronology of all messages processed. In addition to
the stack processing, the memory management logic performs
storage, retrieval, and manipulation functions involving pointer
and message data structures for all three modes.
The BU-65528/27 provides a number of programmable options
for RT mode memory management. In compliance with MIL-
STD-1553, received data from broadcast messages may be
optionally separated from non-broadcast received data. For each
transmit, receive or broadcast subaddress, either a single-mes-
sage data block or a variable-sized (128 to 8192 words) circular
buffer may be allocated for data storage. In addition to helping
ensure data consistency, the circular buffer feature provides a
means of greatly reducing host processor overhead for bulk data
transfer applications. End-of-message interrupts may be enabled
either globally, following error messages, on a Tx/Rx/Bcst-sub-
address basis, or when any particular Tx/Rx/Bcst-subaddress
circular buffer reaches its lower boundary.
BU-65527M AND BU-65527C
The BU-65527M is a Militarized version of the BU-65528 which
is conduction-cooled as per IEEE 1101.2 and is designed to
meet the stringent environmental specifications required by most
military applications.
The BU-65527M routes the 1553 bus connections through the
VME P2 connector. There are no panel-mounted connectors on
the front of the BU-65527X as there are on the BU-65528.
In an effort to eliminate the need for user selectable jumper
blocks (which do not lend themselves to rugged applications) the
register base address of the BU-65527M is selected through
dedicated pins on the VME P2 connector. The 1553 bus connec-
tions on the P2 connector are factory selected for transformer
coupled configuration (contact factory for non-standard direct
coupled configuration). The addressing mode of the BU-
65527M's RAM is factory configured for VME Standard (A24)
Data Device Corporation
www.ddc-web.com
INTERRUPT PROCESSING
Interrupts are enabled by programming the interrupt priority
level, interrupt vector, and interrupt conditions. The interrupt con-
ditions are selected in the interrupt mask register. The BU-
65528/27 generates an interrupt request on the VME/VXI back-
plane and waits for the bus master to initiate an interrupt
acknowledge cycle. Upon receiving an interrupt acknowledge,
the board will place the interrupt vector on bits 7 through 0 of the
data bus and clear the interrupt request. Further interrupts are
disabled until the interrupt is cleared either by an interrupt reset
(in the start reset register) or by reading the interrupt status reg-
ister (if interrupt auto-clear feature is enabled).
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
BU-65528 and BU-65527
F1 web-10/02-0
3
Register provides the current state of the interrupt conditions.
The Interrupt Status Register may be updated in two ways. In
the standard interrupt handling mode, a particular bit in the
Interrupt Status Register will be updated only if the condition
exists and the corresponding bit in the Interrupt Mask Register is
enabled. In the enhanced interrupt handling mode, a particular
bit in the Interrupt Status Register will be updated if the condition
exists regardless of the contents of the corresponding Interrupt
Mask Register bit. In any case, the respective Interrupt Mask
Register bit enables an interrupt for a particular condition.
The BU-65528/27 provides maskable interrupts and 15-bit
Interrupt Status Register for End Of Message(EOM), end-of-BC
message list, erroneous messages, Status Set (BC mode), Time
Tag Register Rollover, RT Address Parity Error conditions, BC
retry, data stack rollover, command stack rollover, transmitter
watchdog timeout, or RAM parity error. The Interrupt Status
Register allows the host processor to determine the cause of all
interrupts by means of a single READ operation.
the bus interface to be VME and adds hardware and software
features which are tailored to test and instrumentation systems.
The key architectural features of the BU-65528/27 over a gener-
ic VME board which make it compliant to VXI are in register def-
inition, memory map of the VME short address space, the map-
ping of device memory into VME standard and extended address
spaces, and the use of the P2 connector.
The VXIbus specification allocates a block of 64 bytes for regis-
ters on each card within the VME Short (A16) address space.
VXI further defines the content and function of the first four 16-
bit registers (ID/Logical address, device type, status/control, and
offset). The remaining 28 words are device dependent.
The entire P1 connector and the middle row of the P2 connector
are defined within the VXIbus standard to be the same as the
definition in the VMEbus standard. The outer rows on the P2 con-
nector, which are user defined in the VMEbus standard, have
specific assignments within the VXIbus standard.
The BU-65528/27 implements the mapping and functionality of
the required VXI registers. This includes the definition of the
memory offset register which is used to program the base
address of the BU-65528/27's buffer memory within the VME
standard (A24) or VME extended (A32) address space.
The BU-65528/27 does not make use of any VXI-defined pins on
the outer rows of the P2 connector and implements the remain-
ing P2 signals and all P1 signals as per the VMEbus specifica-
tion. It should be noted that the militarized BU-65527X card uses
the outer rows of the P2 connector for the 1553 bus signals, RT
address, and register base address. The BU-65527X's device
dependent use of the P2 connector, while fully compliant with the
VMEbus specification, makes it non-compliant with VXIbus stan-
dard.
INTERNAL COMMAND ILLEGALIZATION
The BU-65528/27 offers the option to illegalize commands in RT
mode. The illegalization architecture allows for any subset of the
4096 possible combinations of broadcast/own address,
T / R
bit,
subaddress, and word count/mode code to be illegalized. The
BU-65528/27 illegalization scheme is under software control of
the host processor. As a result, it is inherently self-testable.
INTERNAL TIME TAG
The BU-65528/27 includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64
µs
per
LSB. Another option allows the Time Tag Register to be incre-
mented under software control. This supports self-test for the
Time Tag Register.
For each message processed, the value of the Time Tag register
is loaded into the second location of the respective descriptor
stack entry (“TIME TAG WORD”) for both BC and RT modes.
Additional options are provided to clear the Time Tag Register
following a Synchronize (without data) mode command or load
the Time Tag Register following a Synchronize (with data) mode
command. Another option enables an interrupt request and a bit
in the Interrupt Status Register to be set when the Time Tag
Register rolls over from FFFF to 0000(hex). Assuming the Time
Tag Register is not loaded or reset, this will occur at approxi-
mately 4-second time intervals, for 64
µs/LSB
resolution, down
to 131 ms intervals, for 2
µs/LSB
resolution.
Another programmable option for RT mode is for the Service
Request Status Word bit to be automatically cleared following the
BU-65528/27's response to a Transmit Vector Word mode com-
mand.
ADDRESS MODIFIERS
The address modifiers are programmed as listed in TABLE 2.
TABLE 2. ADDRESS MODIFIERS
ADDRESS
A16
A24
A32
MODIFIERS
29, 2D
3D, 3E, 39, 3A
0D, 0E, 09, 0A
ADDRESSING, INTERNAL REGISTERS, MEMORY
MANAGEMENT, AND INTERRUPTS
ADDRESSING THE BU-65528/27
The software interface of the host processor to a single 1553
channel consists of 22 internal operational registers for normal
operation, an additional 8 test registers, plus 12K x 16 of shared
memory.
The internal registers occupy 64 bytes in the VME/VXI A16
address space while the 12K x 16 of shared RAM resides in
either the A24 or A32 address space. The A24 and A32 support
is software programmable using the I/O address selector pins on
the P2 connector (BU-65527MX is hardwired for A24 address
BU-65528 and BU-65527
F1 web-10/02-0
VME AND VXI
The BU-65528/27 is compliant to both VMEbus and VXIbus.
VXIbus, also referred to as VMEbus Extensions for
Instrumentation, is a functional superset of VMEbus. VXI defines
Data Device Corporation
www.ddc-web.com
4
TABLE 3. A16 ADDRESS MAPPING
HEX ADDRESS
0000,0001
0002,0003
0004,0005
0006,0007
0008,0009
000A,000B
000C,000D
000E,000F
0010,0011
0012,0013
0014,0015
0016,0017
0016,0017
0018.0019
001A,001B
001C,001D
001E,001F
0020,0021
0022,0023
0024,0025
0026,0027
0028,0029
002A,002B
002C,002D
002E,002F
0030,0031
0032,0033
0034,0035
0036,0037
0038,0039
003A,003B
003C,003D
003E,003F
0040,0041
•
•
007E,007F
0080,0081
•
•
00BE,00BF
00C0,00C1
•
•
00FE,00FF
DESCRIPTION/ACCESSIBILITY
ID/Logical Address Register (RD) for Channel #1
Device Type Register (RD) for Channel #1
Status/Control Register (RD/WR) for Channel #1
Offset Register (RD/WR) for Channel #1
Vector/Level (RD/WR) for Channel #1
Reserved
Reserved
Reserved
Interrupt Mask Register (RD/WR) for Channel #1
Configuration Register #1 (RD/WR) for Channel #1
Configuration Register #2 (RD/WR) for Channel #1
Start/Reset Register (WR) for Channel #1
Command Stack Pointer Register (RD) for Ch. #1
BC Ctrl Wd/RT Subaddr Ctrl Wd (RD/WR) for Ch. #1
Time Tag Register (RD/WR) for Channel #1
Interrupt Status Register (RD) for Channel #1
Configuration Register #3 (RD/WR) for Channel #1
Configuration Register #4 (RD/WR) for Channel #1
Configuration Register #5 (RD/WR) for Channel #1
RT/MT Data Stack Addr Reg. (RD/WR) for Ch. #1
BC Frame Time Remaining Register (RD) for Ch. #1
BC Time Remaining to Next Msg Reg. (RD) Ch. #1
BC Frame Time/RT Last Command/MT Trigger Word
Register (RD/WR) for Channel #1
RT Status Word Register (RD) for Channel #1
RT BIT Word Register (RD) for Channel #1
Test Mode Register #0 for Channel #1
Test Mode Register #1 for Channel #1
Test Mode Register #2 for Channel #1
Test Mode Register #3 for Channel #1
Test Mode Register #4 for Channel #1
Test Mode Register #5 for Channel #1
Test Mode Register #6 for Channel #1
Test Mode Register #7 for Channel #1
ID/Logical Address Register for Channel #2
•
•
Test Mode Register #7 for Channel #2
ID/Logical Address Register for Channel #3
•
•
Test Mode Register #7 for Channel #3
ID/Logical Address Register for Channel #4
•
•
Test Mode Register #7 for Channel #4
mode). The base address of the shared RAM within the selected
address space (A24 or A32) is software programmable through
the use of the offset register.
Each 1553 channel contains its own set of independent regis-
ters. The registers for each channel on a card are contiguous.
TABLE 3 illustrates the register address map for a card consist-
ing of four 1553 channels. The register definitions are the same
for each channel. Through the use of the offset register, the
shared memory for each channel may be programmed to have a
unique base address in the A24 or A32 address space.
Definition of the address mapping and accessibility for the BU-
65528/27's 22 non-test registers, and the test registers, is as fol-
lows:
ID/Logical Address Register, and Device Type Register:
Defined by VXI specification. These Read-Only registers are
used to provide device information to the host processor.
Status/Control Register:
Defined by VXI specification. Used to
reset the card and to enable the card's memory.
Offset Register:
Defined by VXI specification. Used to program
the base address of the card's 12K x 16 of shared RAM in either
the A24 or A32 address space.
Vector/Level Register:
Used to program the interrupt priority
level and to define the 8-bit interrupt vector that the card will sup-
ply during an interrupt acknowledge cycle.
Interrupt Mask Register:
Used to enable and disable interrupt
requests for various conditions.
Configuration Registers #1 and #2:
Used to select the BU-
65528/27's mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-on-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
Start/Reset Register:
Used for “command” type functions, such
as software reset, BC/MT Start, Interrupt Reset, Time Tag Reset,
and Time Tag Register Test. The Start/Reset Register includes
provisions for stopping the BC in its auto-repeat mode, either at
the end of the current message or at the end of the current BC
frame.
BC/RT Command Stack Pointer Register:
Allows the host
CPU to determine the pointer location for the current or most
recent message when the BU-65528/27 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register:
In
BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current, or most recent,
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
Data Device Corporation
www.ddc-web.com
5
BU-65528 and BU-65527
F1 web-10/02-0
京公网安备 11010802033920号
EEWORLD
