Target Specification
Datasheet
RNA53A30F
System Organizer IC for Dedicate Microcomputer
Description
RNA53A30F is reset function and reference voltage output for microcontroller has been installed.
Provide support for Renesas MCU operation.
R03DS0034EJ0400
Rev.4.00
Jun 26, 2013
Features
•
•
•
•
•
Reset detection voltage: 3.05 V
±
1%
Standard voltage: 3.050 V
±
0.8%
Delay time: 50,100 ms (fine regulation by resistance is possible)
Corresponds to manual reset
Sleep mode is installed
Ordering Information
Part Name
RNA53A30FUSH1
Package Type
SSOP-8
Package Code
PVSP0008KA-A
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
H (3,000 pcs/reel)
Surface
Treatment
1 (Sn/Bi)
Application
•
Power supply voltage monitoring for microprocessors
•
Computers and notebook computers
•
Digital still camera, digital video camera, and PDA
Block Diagram
VDD
7
SLP
2
ROSC
1
R1
R2
Comp1
+
–
R
Oscillator
5
VOUT
Delay
R
circuit
50 ms
100 ms
OP1
+
–
6 VREFO
I2
I3
4 GND
3
MR
8
S0
R3
Vref
R4
I1
R03DS0034EJ0400 Rev.4.00
Jun 26, 2013
Page 1 of 6
RNA53A30F
Target Specification
Timing Chart
VDD
VSH
tpw = 3 (μs)
min
VDD
Set low pulse width
by value is longer
3
μs.
VS
VSH
VS
MR
GND
VDD
SLP
GND
VDD
VOUT
GND
td
td
td
VREFO
VREFO
GND
uncertainty
0.9
×
td
0.9
×
td
Usually
operation Resetting
AD
operation
operation
0.9
×
td
Usually
operation
AD
operation
AD stop
AD
operation
0.9
×
td
Usually
operation
AD
operation
uncertainty
Microcomputer
operation (reference)
Resetting
operation
Resetting
operation
Resetting
operation
R03DS0034EJ0400 Rev.4.00
Jun 26, 2013
Page 2 of 6
RNA53A30F
Target Specification
Pin Arrangement
ROSC
SLP
MR
GND
1
2
3
4
(Top view)
8
7
6
5
S0
VDD
VREFO
VOUT
Mark Indication
(1) (2) (3)
N 0 3
(1)
(2)
(3)
Year code
Month code
Week code
The last digit of year
Starting in January "A", "B", "C", "D", "E", "F", "G", "H", "J", "K", "L", "M"
View week of month, 1 week
→
"1"
Pin Description
Pin No.
1
2
Terminal
Marking
ROSC
SLP
Terminal Name
Oscillation control resistance
installation terminal
Sleep mode control
I/O
—
I
Function
3
MR
Manual reset input
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.1 MΩ is installed between GND usually.
Delay adjustment range of resistance: 650(kΩ) to 1.35(MΩ)
L: Sleep mode (Power-supply current becomes several
μA)
H: Usually mode
Terminal is open, Pull-down in GND
Low is input, 5pin(VOUT) output the low level
Set the low pulse width by value is longer 3
μs
Terminal open, pull-up in VDD
Sorcing 0 V.
Power-supply voltage reaches the value below the detection
voltage, low is output
Low level is input to
MR
terminal, low is output
Open drain output
Range pull-up resistance: 10(kΩ) to 100(kΩ)
Standard voltage (3.05 V typ) for AD/DA is output
Outside puts capacity (0.1
μF)
by pursuant for microcomputer
Sorcing power-supply voltage.
Delay time is switched. Low: 50 (ms), High: 100 (ms)
Terminal is open, pull-up in Vdd
4
5
GND
VOUT
GND
Reset output
—
O
6
7
8
VREFO
VDD
S0
Standard voltage output
Power-supply terminal
Delay time switch
O
—
I
R03DS0034EJ0400 Rev.4.00
Jun 26, 2013
Page 3 of 6
RNA53A30F
Target Specification
Absolute Maximum Ratings
Item
Supply voltage
Output voltage (open-drain type)
Input voltage
Output current
Standard voltage terminal source current
Continuous power dissipation
Operating temperature
Storage temperature
VDD
Vout
Vin
Iout
IREF
Pd
Topr
Tstg
Symbol
Ratings
6.5
–0.3 to +6.5
–0.3 to VDD
10
5
160 (Ta = 25°C)
–40 to +85
–55 to +125
Unit
V
V
V
mA
mA
mW
°C
°C
Electrical Characteristics
(Vdd = 3.3 V, Ta = 25°C, unless otherwise noted)
Item
Output fixation
voltage
Operating limit
voltage
Current consumption
Standing circuit
current
Detecting voltage
Detecting voltage
temperature
coefficient
Hysteresis voltage
Standard voltage
Standard voltage
temperature
coefficient
Standard voltage
return time
Output low voltage
Output leakage
current
Minimum pulse width
Delay time
Reactive time
High input voltage
Low input voltage
S0 terminal pull-up
current
MR
terminal pull-up
current
SLP
terminal pull-
down current
Symbol
VOUL
VOPM
Idd
IddSLP
VS
Vs/ΔT
Min
—
2.7
—
—
3.019
—
Typ
—
—
100
2.8
3.049
±100
Max
0.9
—
200
5.6
3.079
—
Unit
V
V
μA
μA
V
ppm/°C
Vdd = 3.3 V,
SLP
= Hi (Vdd)
SLP
= Low (GND),
MR
= Hi (Vdd),
S0
= Hi (Vdd)
Test Conditions
VOUT
terminal, RL = 10 (kΩ)
VHYS
VREF
VREF/
ΔT
VRCV
VOL
ILK
tpw
td
tPHL
VIH
VIL
IPUS0
IPUMR
IPDSLP
VS×0.01
3.026
—
VS×0.02
3.050
±100
VS×0.03
3.074
—
V
V
ppm/°C
Vdd
≥
3.3 V, Isource = 0 to 3 mA,
CL = 0.1
μF
—
—
—
3
35
70
—
Vdd×0.8
0
—
1.5
—
—
0.3
—
—
50
100
6
—
—
—
3
—
0.9×td
0.54
100
—
65
130
—
Vdd
Vdd×0.2
0.5
6
0.5
ms
V
nA
μs
ms
ms
μs
V
V
μA
μA
μA
VOUT,
Isink = 4 mA, Vdd = 2.6 (V)
VOUT,
Vdd = 3.6 V
MR terminal input
S0 = Low
S0 = High
VDD drop to time until outputting
VOUT
MR
input to time until outputting
VOUT
MR
terminal,
SLP
terminal, S0 terminal,
Vdd = 3.0 V to 3.6 V
MR
terminal,
SLP
terminal, S0 terminal,
Vdd = 3.0 V to 3.6 V
S0 terminal
MR
terminal
SLP
terminal
R03DS0034EJ0400 Rev.4.00
Jun 26, 2013
Page 4 of 6
RNA53A30F
Target Specification
Example of Application Circuit
[Application Example1]
Vdd
VDD
7
Interrupt
signal
SLP
2
ROSC
1
R8
R9
R1
R2
Comp1
+
–
R
Oscillator
Reset signal output to
external systems
Vdd
IRQ#
Delay
R
circuit
50 ms
100 ms
5
VOUT
RES#
Microcomputer
OP1
+
–
Vref
I2
R4
R3
I1
I3
6
VREFO
VREFH
0.1
μF
t
WL2
WDTOVF#
VREFL (GND)
4
GND
3
MR
Reset signal from another
system, and manual reset
EX-NOR
8
S0
(1)
Such t
WL1
> t
WL2
, (1) recommend set a longer pulse width.
Low pulse between two is recommended set to overlap.
t
WL1
[Application Example2]
Vdd
VDD
7
Interrupt
signal
SLP
2
ROSC
1
R8
R9
R1
R2
Comp1
+
–
R
Oscillator
Reset signal output to
external systems
Vdd
IRQ#
Delay
R
circuit
50 ms
100 ms
5
VOUT
RES#
Microcomputer
OP1
+
–
Vref
I2
R4
R3
I1
I3
6
VREFO
VREFH
0.1
μF
VREFL (GND)
4
GND
3
MR
(1)
(2)
(3)
8
S0
Reset signal from another
system, and manual reset
R03DS0034EJ0400 Rev.4.00
Jun 26, 2013
Page 5 of 6
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