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DATA SHEET
µ
PD703037A, 703037AY,
70F3037A, 70F3037AY
V850/SB2
32-BIT SINGLE-CHIP MICROCONTROLLERS
TM
MOS INTEGRATED CIRCUITS
DESCRIPTION
The
µ
PD703037A, 703037AY, 70F3037A, and 70F3037AY (V850/SB2) are 32-bit single-chip microcontrollers of
the V850 Series
TM
for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter, DMA
controller, and so on are integrated on a single chip.
The
µ
PD70F3037A and 70F3037AY have flash memory in place of the internal mask ROM of the
µ
PD703037A
and 703037AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
The
µ
PD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY products with a different
ROM/RAM size are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
TM
V850/SB1 , V850/SB2 User’s Manual Hardware: U13850E
V850 Series User’s Manual Architecture:
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
General-purpose registers: 32 bits
×
32 registers
Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
Memory space: 16 MB linear address space
Internal memory ROM: 512 KB (
µ
PD703037A, 703037AY: mask ROM)
512 KB (
µ
PD70F3037A, 70F3037AY: flash memory)
RAM: 24 KB (
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY)
Interrupt/exception:
µ
PD703037A, 70F3037A (external: 8, internal: 33 sources, exception: 1 source)
µ
PD703037AY, 70F3037AY (external: 8, internal: 34 sources, exception: 1 source)
I/O lines Total: 83
Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
Watch timer: 1 channel
Watchdog timer: 1 channel
IEBus
TM
controller: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14894EJ2V0DS00 (2nd edition)
Date Published February 2002 J CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY
Serial interface
•
Asynchronous serial interface (UART0, UART1)
•
Clocked serial interface (CSI0 to CSI3)
•
3-wire variable length serial interface (CSI4)
•
I C bus interface (I C0, I C1) (
µ
PD703037AY, 70F3037AY only)
2
2
2
10-bit resolution A/D converter: 12 channels
DMA controller: 6 channels
Real-time output port: 8 bits
×
1 channel or 4 bits
×
2 channels
ROM correction: 4 places can be corrected
Power-saving function: HALT/IDLE/STOP modes
Packages: 100-pin plastic QFP (14
×
20)
µ
PD70F3037A, 70F3037AY
•
Can be replaced with
µ
PD703037A and 703037AY (internal mask ROM) in mass production
APPLICATIONS
AV equipment (audio, car audio, VCR, TV, etc.)
ORDERING INFORMATION
Part Number
×××-3BA
µ
PD703037AGF-×××
×××
×××-3BA
µ
PD703037AYGF-×××
×××
Package
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
Internal ROM
Mask ROM (512 KB)
Mask ROM (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
µ
PD70F3037AGF-3BA
µ
PD70F3037AYGF-3BA
Remarks 1.
×××
indicates ROM code suffix.
2.
ROMless versions are not provided.
2
Data Sheet U14894EJ2V0DS
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